Abstract: A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.

Abstract: A monolithic active pixel radiation detector including a method of fabricating thereof. The disclosed radiation detector can include a substrate comprising a silicon layer upon which electronics are configured. A plurality of channels can be formed on the silicon layer, wherein the plurality of channels are connected to sources of signals located in a bulk part of the substrate, and wherein the signals flow through electrically conducting vias established in an isolation oxide on the substrate. One or more nested wells can be configured from the substrate, wherein the nested wells assist in collecting charge carriers released in interaction with radiation and wherein the nested wells further separate the electronics from the sensing portion of the detector substrate. The detector can also be configured according to a thick SOA method of fabrication.

Abstract: A method for producing an optoelectronic component comprising the steps of providing a semiconductor layer sequence having at least one active region, wherein the active region is suitable for emitting electromagnetic radiation during operation, and applying at least one layer on a first surface of the semiconductor layer sequence by means of an ion assisted application method.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: Provided is an organic light-emitting display apparatus including a substrate; and a plurality of pixels on the substrate, wherein each of the pixels comprise: an organic light-emitting device comprising a first electrode, a second electrode, and an intermediate layer between the first electrode and the second electrode, wherein the intermediate layer comprises an organic emission layer; a driving transistor configured to drive the organic light-emitting device; and a switching transistor electrically coupled to the driving transistor, wherein the gate electrode of the driving transistor comprises a first conductive layer, and a second conductive layer between the first conductive layer and the active layer of the driving transistor and has a smaller size than the first conductive layer, and the gate electrode of the switching transistor comprises a same material as the first conductive layer.

Abstract: A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode.

Abstract: The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. Furthermore, the first transistor provided in the driver circuit portion may include the oxide semiconductor film in which a first film and a second film are stacked, and the second transistor provided in the pixel portion may include the oxide semiconductor film which differs from the first film in the atomic ratio of metal elements.

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract: A fluorescent material according to an aspect of the present disclosure mainly comprises a compound represented by AB0.5-w-x-y-zCwEuxSmyLnzW0.5O3. A is one or more elements selected from the group consisting of alkaline earth metals and mainly contains Ca. B is one or more elements selected from the group consisting of divalent metals and mainly contains Mg. C is one or more elements selected from the group consisting of alkali metals and mainly contains Li, Na, or Li and Na. Ln is one or more elements selected from the group consisting of rare earth elements excluding Eu and Sm. w, x, y, and z meet the following conditions: 0.05?w?0.25, 0.05?x+y?0.25, 0.0?y?0.02, and w=x+y+z.

Abstract: The present invention relates to a method for manufacturing an epitactic silicon layer made up of crystallites with a size no lower than 20 ?m, including: providing a layer of crystallized silicon the surface of which, being inhomogeneous in terms of the size of the crystallites, is made up of large crystallites with a size no lower than 20 ?m, and small crystallites of a smaller size; forming, on the surface of the inhomogeneous silicon layer, a layer of at least one non-nucleating material for the silicon, the thickness of which is adjusted such to cover the entire outer surface of the small crystallites, while leaving all or part of the outer surface of the large crystallites accessible; and carrying out epitaxial growth of a silicon layer on the surface of the assembly obtained at the end of step, under conditions that are suitable for forming the expected epitactic layer.

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract: An organic light emitting display device includes a thin film transistor on a substrate, a first protection layer covering the thin film transistor, a conductive organic layer on the first protection layer and coupled to the thin film transistor, and an organic light emitting device on the conductive organic layer and coupled to the conductive organic layer.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: A substrate is diced using a program-controlled pulsed laser beam apparatus having an associated memory for storing a laser cutting strategy file. The file contains selected combinations of pulse rate ?t, pulse energy density E and pulse spatial overlap to machine a single layer or different types of material in different layers of the substrate while restricting damage to the layers and maximizing machining rate to produce die having predetermined die strength and yield. The file also contains data relating to the number of scans necessary using a selected combination to cut through a corresponding layer. The substrate is diced using the selected combinations. Gas handling equipment for inert or active gas may be provided for preventing or inducing chemical reactions at the substrate prior to, during or after dicing.

Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

Abstract: A semiconductor device includes an epitaxial layer including a first surface and a silicon layer disposed on the first surface and including a second surface opposite to the first surface, wherein the silicon layer includes a plurality of pillars on the second surface, a portion of the plurality of pillars on a predetermined portion of the second surface are in substantially same dimension, each of the plurality of pillars on the predetermined portion of the second surface stands substantially orthogonal to the second surface, the plurality of pillars are configured for absorbing an electromagnetic radiation of a predetermined wavelength projected from the epitaxial layer and generating an electrical energy in response to the absorption of the electromagnetic radiation.

Abstract: The invention provides an array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device. The array substrate includes a display region and a non-display region, wherein a plurality of data signal lines are provided in the display region, and a plurality of connection terminal pads and a plurality of metal wires connecting the connection terminal pads with the respective data signal lines are provided in the non-display region, wherein at least one blocking part covering the plurality of metal wires is provided above the plurality of metal wires. In the array substrate of the invention, as the at least one blocking part covering the metal wires is provided above the metal wires, which can block foreign objects from contacting the metal wires, thus the cutting debris can be prevented from scratching the metal wires in the cutting process.