Abstract: A connection carrier for at least one semiconductor chip is disclosed. The connection carrier has a carrier body having a main surface. A first connection area and a second connection area at a distance from the first connection area are formed on the main surface. The connection carrier has a mechanical decoupling device which is intended to reduce transmission of mechanical forces from the carrier body to at least one region of the first connection area. A semiconductor component having such a connection carrier is also stated.

Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

Abstract: A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region.

Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

Abstract: An RF LDMOS device is disclosed, including: a substrate having a first conductivity type; a channel doped region having the first conductivity type and a drift region having a second conductivity type, each in an upper portion of the substrate, the channel doped region having a first end in lateral contact with a first end of the drift region; a first well having the first conductivity type in the substrate, the first well having a top portion in contact with both of a bottom of the first end of the channel doped region and a bottom of the first end of the drift region; and a second well having the first conductivity type in the substrate, the second well having a top portion in contact with a bottom of a second end of the drift region. A method of forming such an RF LDMOS device is also disclosed.

Abstract: Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.

Abstract: A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.

Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract: Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Abstract: A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well.

Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

Abstract: A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well.

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract: An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode.

Abstract: The present disclosure relates to a hybrid organic-inorganic thin film producing method including an interlayer connection between an inorganic cross-linked layer and an organic polymer through a molecular layer deposition (MLD) method, a hybrid organic-inorganic thin film produced by the producing method, and an organic electronic device and a thin film transistor containing the hybrid organic-inorganic thin film.

Abstract: A radiation-emitting semiconductor component includes a light-emitting diode chip with at least two emission regions that can be operated independently of each other and at least two differently designed conversion elements. During operation of the light-emitting diode chips each of the emission regions is provided for generating electromagnetic primary radiation. Each emission region has an emission surface by which at least part of the primary radiation is decoupled from the light-emitting diode chip. The conversion elements are provided for absorbing at least part of the primary radiation and for re-emitting secondary radiation. The differently designed conversion elements are disposed downstream of different emission surfaces. An electric resistance element is connected in series or parallel to at least one of the emission regions.

Abstract: A phase-change nonvolatile memory (PRAM) is constituted of a semiconductor substrate, a lower electrode, a first interlayer insulating film having a first hole, an impurity diffusion layer embedded in the first hole, a second interlayer insulating film having a second hole whose diameter is smaller than the diameter of the first hole, a phase-change recording layer, and an upper electrode. The impurity diffusion layer is constituted of two semiconductor layers having different conductivity types, wherein one semiconductor layer is constituted of a base portion and a projecting portion having a heating spot in contact with the phase-change recording layer, while the other semiconductor layer is formed to surround the projecting portion. A depletion layer is formed in proximity to the junction surface so as to reduce the diameter of the heating spot, thus reducing the current value Ireset for writing data in to the phase-change recording layer.