Abstract: In a general aspect, a circuit can include a pass device configured to receive an input voltage and provide an output voltage. The circuit can further include a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage. The circuit can also include a switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage.

Abstract: A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

Abstract: In certain aspects, a driver includes a pull-down transistor coupled between an output and a ground, a pull-up n-type field effect transistor (NFET) coupled between a first voltage rail and the output, and a pull-up p-type field effect transistor (PFET) coupled between the first voltage rail and the output. The driver also includes a first switch coupled between a gate of the pull-up NFET and the ground, and a second switch coupled between a gate of the pull-up PFET and a second voltage rail.

Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.

Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

Abstract: An inverter for wireless power transfer includes a primary inverter connected in series with a first primary inductor. A first primary capacitor is connected in parallel with the first primary inductor and primary inverter. A series-connected second primary capacitor and primary pad inductor are in parallel with the second primary capacitor. The synchronous inverter includes a controller configured to detect a first primary current in the first primary inductor to control switches in the primary inverter to provide a positive primary inverter voltage across the output of the primary inverter in response to detecting a positive first primary current, and control the switches in the primary inverter to provide a negative primary inverter voltage across the output of the primary inverter in response to detecting a negative first primary current.

Abstract: An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible.

Abstract: A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.

Abstract: A drive circuit performs switching between an on-state and an off-state of a PIN diode, the drive circuit being provided with a switching element and a switching element, a drive power supply, and a current limiting resistor that adjusts a forward current of the PIN diode. When the switching element is in an on-state and the switching element is in an off-state, the PIN diode is switched to the on-state by applying a forward voltage to the PIN diode from the drive power supply via the current limiting resistor, and when the switching element is in the off-state and the switching element is in the on-state, the PIN diode is switched to the off-state by applying, not via the current limiting resistor, a reverse voltage to the PIN diode from the drive power supply.

Abstract: Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.

Abstract: Apparatus and methods for control and calibration of tunable filters are provided. In certain embodiments, a tunable filter includes at least one controllable component (for instance, a controllable inductor or a controllable capacitor) having a value that changes or adjusts a center frequency of the tunable filter. For example, the controllable component can correspond to a controllable inductor or a controllable capacitor of an inductor-capacitor (LC) resonator of the tunable filter. The tunable filter further includes a control circuit implemented with an approximation function for estimating a value of the controllable component for achieving a desired center frequency indicated by a frequency control signal.

Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.

Abstract: A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

Abstract: An inductive-capacitive filter includes a first insulating-conductive strip wound around a winding axis, where the first insulating-conductive strip includes a first conductive strip joined with a first insulating strip. An inductive-capacitive filter assembly includes a first and a second insulating-conductive strip concentrically wound around a winding axis, the first insulating-conductive strip including a first conductive strip joined with a first insulating strip, and the second insulating-conductive strip including a second conductive strip joined with a second insulating strip.

Abstract: A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor generates a mechanical force that drives a component. A ripple count circuit is configured to filter the drive current based on a rotational speed (?) of the rotor, and to generate a pulsed output signal indicative of the rotational speed (?) of the rotor and a rotational position (?) of the rotor.

Abstract: A level shifter comprising: a translation circuit having two input lines and two output lines and configured to receive a differential signal in a low-voltage domain on the two input lines and provide a second differential signal, being a copy of the first differential signal, in a high-voltage domain on the two output lines; and a combiner circuit configured to convert the second differential signal into a single-ended signal at a high-voltage shifter output; wherein the combiner circuit comprises a two-input Muller C-element circuit wherein one input is inverted. Corresponding methods are also disclosed.

Abstract: A bidirectional power conversion system includes three power conversion ports. A first power conversion port includes a power factor correction device and a primary power conversion network. A second power conversion port includes a plurality of switches and a plurality of diodes, wherein an output voltage of the second power conversion port is regulated through adjusting an output voltage of the power factor correction device as well as through adjusting an operating parameter of the primary power conversion network. A third power conversion port includes a first switch network and a power regulator connected in cascade, wherein the first power conversion port, the second power conversion port and the third power conversion port are magnetically coupled to each other through a transformer.

Abstract: A molten metal fuel to plasma to electricity power source and an element of a communication network that provides at least one of electrical and thermal power and a portal for transmission of information comprising (i) at least one reaction cell for the catalysis of atomic hydrogen to form hydrinos, (ii) a chemical fuel mixture comprising at least two components chosen from: a source of H2O catalyst or H2O catalyst; a source of atomic hydrogen or atomic hydrogen; reactants to form the source of H2O catalyst or H2O catalyst and a source of atomic hydrogen or atomic hydrogen; and a molten metal to cause the fuel to be highly conductive, (iii) a fuel injection system comprising an electromagnetic pump, (iv) at least one set of electrodes that confine the fuel and an electrical power source that provides repetitive short bursts of low-voltage, high-current electrical energy to initiate rapid kinetics of the hydrino reaction and an energy gain due to forming hydrinos to form a brilliant-light emitting plasma, (v)