Abstract: A driver circuit for switching edge modulation of a power switch. The driver circuit includes a first driver circuit input including a downstream input node, and a power switch including an upstream first gate node. A charging path including a charging resistor is situated between the input node and the first gate node. A discharging path including a discharging resistor is situated between the input node and the first gate node. A gate path is situated between the input node and the first gate node. A power switch transistor, whose gate is connected to the first gate node, is provided. A gate path includes a gate resistor. The driver circuit is configured so that, during a switching process of the power switch, the gate path is temporarily short-circuited either via the charging path or the discharging path, to increase the slope of the switching behavior of the power switch.

Abstract: In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Abstract: A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.

Abstract: Disclosed is a power distribution system, comprising a power feed line configured to supply electric power of a given power feed line voltage, a plurality of solid state power control modules connected to the power feed line; each of the solid state power control modules comprising at least one solid state power controller connected to at least one load to be supplied with power from the power feed line and configured to selectively connect the respective load to the power feed line or to disconnect the respective load from the power feed line; the power feed line comprising at least one power feed line segment connecting two adjacent solid state power control modules; wherein the at least two adjacent solid state power control modules are connected by a further electric line connected in parallel to the at least one power feed line segment.

Abstract: Provided are a transmission line module for a rotary traveling wave oscillator (RTWO) and a design method thereof. The transmission line module includes a substrate. The upper surface of the substrate is provided with a grounding metal layer, that is, a metal ground. The metal ground is provided with a rectangular groove. The rectangular groove penetrates front and rear sides of the metal ground along a length direction of the rectangular groove. The thickness of the rectangular groove is the same as the thickness of the metal ground. The rectangular groove is filled with a silicon dielectric plate that has the same shape and size as the rectangular groove. The upper surface of the silicon dielectric plate is provided with two parallel transmission lines along the length direction of the rectangular groove.

Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, a first switch, and a second switch. The first differential input pair receives an output voltage at an output node and a first temperature-dependent voltage. The second differential input pair receives the output voltage and a second temperature-dependent voltage. When the output voltage reaches the second temperature-dependent voltage, the first switch is turned on to pull up the output voltage in response to a first control signal generated according to an output signal of the second differential input pair. When the output voltage reaches the first temperature-dependent voltage, the second switch is turned on to pull down the output voltage in response to a second control signal generated according to an output signal of the first differential input pair.

Abstract: An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

Abstract: This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

Abstract: A resistance welder controller controls a welding current flowing through an inverter transformer, detects the welding current flowing through the inverter transformer, measures an energizing time and a point time interval of the detected welding current, calculates a usage rate of the inverter transformer using the energizing time and the point time interval, stores an equivalent current curve indicating a relationship between a current value of the welding current and the usage rate of the inverter transformer when the inverter transformer is operated at a rated capacity, and determines whether a relationship between the current value and the calculated usage rate of the inverter transformer exceeds the rated capacity of the inverter transformer based on the equivalent current curve, continues an operation when the relationship does not exceed the rated capacity of the inverter transformer, and stops the operation when the relationship exceeds the rated capacity of the inverter transformer.

Abstract: A switch circuit of an embodiment includes a high frequency switch, a first charge pump circuit, a boost signal generation circuit, and a second charge pump circuit. The high frequency switch switches transmission and reception of a high frequency signal. The first charge pump circuit generates a first voltage and a second voltage biased to the high frequency switch. When an edge of an input signal is detected, the boost signal generation circuit generates a first boost signal for temporarily increasing drive capacity of the first charge pump circuit. When the first boost signal is input, the second charge pump circuit operates to temporarily increase the drive capacity of the first charge pump circuit.

Abstract: A switchable element, a device and a method for analogue and programmable computing operating on electromagnetic waves having a frequency, wherein the switchable element is configured to configured to, in response to an activation signal, switch from having a first dielectric permittivity for electromagnetic waves having a frequency to having a second dielectric permittivity for electromagnetic waves having the frequency, and the device comprises a plurality of the switchable elements that are adapted to be switched individually in accordance with the computing operation.

Abstract: A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

Abstract: Disclosed is a device for filtering electrical noise in a vehicle. The device includes a housing connectable to the vehicle, a variable capacitor, an input signal line coupled to the variable capacitor and couplable to a first conductor that carries electrical signals along with electrical noise of a given amplitude, and an output signal line coupled to the variable capacitor and couplable to a second conductor. When the input signal line is coupled to the first conductor and the output signal line is coupled to the second conductor, the second conductor carries the electrical signals along with electrical noise of reduced amplitude within a range of frequencies. The device also includes a tuner coupled to the housing and configured to adjust a capacitance of the variable capacitor, wherein adjusting the capacitance of the variable capacitor adjusts the range of frequencies.

Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Abstract: Circuit embodiments for a switched-capacitor power converter, and/or methods of operation of such a converter, that robustly deal with various startup scenarios, are efficient and low cost, and have quick startup times to steady-state converter operation. Embodiments prevent full charge pump capacitor discharge during shutdown of a converter and/or rebalance charge pump capacitors during a startup period before switching operation by discharging and/or precharging the charge pump capacitors. Embodiments may include a dedicated rebalancer circuit that includes a voltage sensing circuit coupled to an output voltage of a converter, and a balance circuit configured to charge or discharge each charge pump capacitor towards a target steady-state multiple of the output voltage of the converter as a function of an output signal from the voltage sensing circuit indicative of the output voltage. Embodiments prevent or limit current in-rush to a converter during a startup state.

Abstract: A method for selecting a power source for a load is provided. The method includes monitoring the primary power source, when the primary power source is providing power to the load, determining if a condition of the primary power source crosses a first threshold, when the condition crosses the first threshold, turning on a first power field effect transistor to couple a back-up power source to the load through a second power field effect transistor, when the primary power source is not providing power to the load, determining if a condition of the primary power source crosses a second threshold, and when the condition crosses the second threshold, switching off the first power field effect transistor to couple the primary power source to the load through a third power field effect transistor.