Abstract: The disclosure relates to an electrical component, for example, a surface-mount resonator, including a distributed-element circuit disposed on a dielectric base and separated from an electromagnetic field modification member by a gaseous gap, wherein a frequency characteristic of the electrical component can be tuned by positioning the electromagnetic field modification member relative to the distributed-element circuit using an actuator.

Abstract: A superconducting device that mixes surface acoustic waves and microwave signals and techniques for fabricating the same are provided. A superconducting device can comprise a superconducting surface acoustic wave resonator and a superconducting microwave resonator. The superconducting device can also comprise a Josephson ring modulator coupled to the superconducting surface acoustic wave resonator and the superconducting microwave resonator. The Josephson ring modulator can be a dispersive nonlinear three-wave mixing element.

Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/?3VV, +/?VV/5 or +/?VV/6.

Abstract: A power converter with an inverter that is configured to transform electrical power between a DC-side of the power converter and an AC-side of the power converter, includes a first port operatively connected to an AC-grid, a second port operatively connected to an AC-load, a third port connected to an external power source, and a fourth port operatively connected to a rechargeable DC-power storage. The power converter includes a DC/DC-converter between the third port and the inverter, to transfer electrical power provided by the external power source from the third port to the inverter. The inverter is configured to be grid forming and provide electrical power to the second port upon a power supply outage at the first port, the power converter includes a control unit to monitor the third port and detect parameters of the electrical power provided via the third port.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: A current mode control modulation includes a ramp signal generator generating a slope compensated ramp signal with slope compensation. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator includes a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit to generate the ramp signal with slope compensation.

Abstract: In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

Abstract: The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.

Abstract: A method for providing at least one of the following information to an athlete during a race such as a running or a cycling race: a race time prediction; a probability to achieve a target time at the end of the race; and/or an indication whether the pace followed by the athlete is too fast, adequate or too slow in order to achieve a target time. The method includes measuring during the race a plurality of intermediate times with an inertial sensor and/or a positional sensor in a wearable device; causing a processing unit in the wearable device to retrieve, based on the intermediate time and on previous races of other athletes, a race profile as non-linear function of time over distance (t=f(d)); and using the retrieved race profile for determining the information.

Abstract: Phase shifters such as networks that can be used in MMIC (Monolithic Microwave Integrated Circuit) and hybrid digital phase shifters, for low loss, wide bandwidth, and high linearity. A digital phase shifter includes input port for receiving signals and output ports for transmitting the signals. Multiple transmission lines are arranged between the input and output ports of the phase shifter. The transmission lines are arranged in a ring with first pair of the transmission lines which are arranged in series in a first path and second pair of the transmission lines arranged in series in a second path. One of the transmission lines of the first and second pairs include quarter-wave hybrid coupled line with coupled-ports and through-ports terminated in short-circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: The present disclosure refers to a waveguide electromechanical relay switch having a rotor with transmission paths and an axis of rotation parallel to the base plane combined with an actuator adapted to the configuration. A 4-pol switch design enables compensation of fault cases in a relatively shortened length of transmission line, reducing potential RF loss. In one embodiment, a 4-pol rotor includes an offset transmission path that enables crossing of another path on the same rotor, providing increased functionality and fault-case recovery.

Abstract: An electrical power converter can include a plurality of layers disposed on a substrate. An emitter, including a first semiconductor junction that is formed at an interface between a first pair of adjacent layers, can produce light in response to a first electrical signal. An absorber, including a second semiconductor junction that is formed at an interface between a second pair of adjacent layers, can absorb at least some of the light. Circuitry can produce a second electrical signal in response to the absorbed light. The second electrical signal can be substantially proportional to the first electrical signal and can be electrically isolated from the first electrical signal. Because the light can remain within the layers during use, the electrical power converter can have a higher efficiency than a comparable device that propagates the light through at least one interface between air and a semiconductor material.

Abstract: An auto safety jumper module to prevent accidental short circuits or wrong connections between a jump start system and a motor vehicle battery when jump starting such motor vehicle. The module can be fully automatic and capable of detecting when a motor vehicle battery is connected to it. The module, which can be integrated into or an external add-on to a jump start system, does not need an external sensing wire(s) to detect when alligator clamps of the jump start system are connected to a vehicle battery post or to detect when the alligator clamps are disconnected.

Abstract: Methods, systems, and apparatus for implementing a unitary quantum gate on one or more qubits. In one aspect, a method includes the actions designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced; generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.

Abstract: A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/?3VV, +/?VV/5 or +/?VV/6.

Abstract: A driver circuit for switching edge modulation of a power switch. The driver circuit includes a first driver circuit input including a downstream input node, and a power switch including an upstream first gate node. A charging path including a charging resistor is situated between the input node and the first gate node. A discharging path including a discharging resistor is situated between the input node and the first gate node. A gate path is situated between the input node and the first gate node. A power switch transistor, whose gate is connected to the first gate node, is provided. A gate path includes a gate resistor. The driver circuit is configured so that, during a switching process of the power switch, the gate path is temporarily short-circuited either via the charging path or the discharging path, to increase the slope of the switching behavior of the power switch.

Abstract: In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Abstract: A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.