Patents Examined by Hai Pham
-
Patent number: 8391050Abstract: To provide a resistance change element which can reduce the current required to switch the state to the high resistance state from the low resistance state. The resistance change element according to the exemplary embodiment includes three or more electrodes, none of the electrodes supplying ion to a resistance change material (205). It includes a material (206) which does not show resistance change arranged between an electrode (207) and the resistance change material (205), and current pathways formed at two electrodes (204) other than the electrode (207).Type: GrantFiled: March 18, 2009Date of Patent: March 5, 2013Assignee: NEC CorporationInventor: Kimihiko Ito
-
Patent number: 8379437Abstract: Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.Type: GrantFiled: August 31, 2009Date of Patent: February 19, 2013Assignee: SanDisk 3D, LLCInventors: Tyler Thorp, Roy E. Scheuerlein
-
Patent number: 8379435Abstract: An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently.Type: GrantFiled: July 22, 2009Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: Russell C. McMullan, Theodore W. Houston
-
Patent number: 8363498Abstract: A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines such that a read or write operation of data is achieved in each mat, a column switching unit configured to select any one of bit lines from among the plurality of bit lines according to a column selection signal, and selectively control a connection between the selected bit line and a global bit line, and a discharge unit, in an active mode in which the read or write operation is achieved, configured to discharge the remaining bit lines other than the selected bit line from among the plurality of bit lines in response to a bit line discharge signal.Type: GrantFiled: June 25, 2010Date of Patent: January 29, 2013Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Wook Park
-
Patent number: 8364913Abstract: A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data.Type: GrantFiled: July 29, 2010Date of Patent: January 29, 2013Assignee: SK Hynix Inc.Inventor: Seung Wook Kwak
-
Patent number: 8345507Abstract: A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section.Type: GrantFiled: September 28, 2010Date of Patent: January 1, 2013Assignee: Seiko Epson CorporationInventors: Shinichi Yamada, Yasuhiko Kosugi, Noboru Asauchi, Yoshihiro Nakamura
-
Patent number: 8345469Abstract: A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition.Type: GrantFiled: September 16, 2010Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, Ravindraraj Ramaraju
-
Patent number: 8339847Abstract: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N?1)th page programming operations, using an incremental step pulse programming (ISPP) method, to program first through (N?1)th data pages in the MLC memory cells, where each of the first through (N?1)th page programming operations includes an erase programming of erase cells among the MLC memory cells. The method further includes executing an Nth page programming operation, using the ISPP method, to program an Nth data page in the MLC memory cells.Type: GrantFiled: August 24, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Youngho Lim, Dongku Kang, HyeongJun Kim
-
Patent number: 8339844Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.Type: GrantFiled: March 12, 2008Date of Patent: December 25, 2012Assignee: eASIC CorporationInventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
-
Patent number: 8339845Abstract: Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.Type: GrantFiled: March 8, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Oh Suk Kwon
-
Patent number: 8331121Abstract: A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time.Type: GrantFiled: February 23, 2010Date of Patent: December 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: YoungSeok Hong
-
Patent number: 8325554Abstract: A memory module is provided comprising a substrate having an interface to a host system, volatile memory, non-volatile memory, and a logic device. The logic device may receive the indicator of an external triggering event and copies data from the volatile memory devices to the non-volatile memory devices upon receipt of such indicator. When the indicator of the triggering event has cleared, the logic device restores the data from the non-volatile to the volatile memory devices. The memory module may include a passive backup power source (e.g., super-capacitor) that is charged by an external power source and temporarily provides power to the memory module to copy the data from volatile to non-volatile memory. A voltage detector within the memory module may monitor the voltage of an external power source and generates an indicator of a power loss event if voltage of the external power source falls below a threshold level.Type: GrantFiled: July 9, 2009Date of Patent: December 4, 2012Assignee: Sanmina-Sci CorporationInventors: Paul Sweere, Jonathan R. Hinkle
-
Patent number: 8325532Abstract: A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.Type: GrantFiled: April 5, 2010Date of Patent: December 4, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Eiichi Makino
-
Patent number: 8315093Abstract: Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.Type: GrantFiled: February 15, 2012Date of Patent: November 20, 2012Assignee: SanDisk Technologies Inc.Inventors: Yingda Dong, Tien-chien Kuo, Gerrit Jan Hemink
-
Patent number: 8310866Abstract: A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.Type: GrantFiled: July 7, 2008Date of Patent: November 13, 2012Assignees: Qimonda AG, ALTIS Semiconductor, SNCInventors: Rainer Leuschner, Ulrich Klostermann, Richard Ferrant
-
Patent number: 8305824Abstract: In some embodiments a voltage regulator provides an operation voltage to a memory system and a transient voltage supply adjusts the operation voltage provided by the voltage regulator during transient events of the memory system. Additionally, the voltage supply may adjust the operation voltage provided to the memory system at a fixed time interval that corresponds to a worst case load transient event.Type: GrantFiled: April 8, 2009Date of Patent: November 6, 2012Inventor: Lilly Huang
-
Patent number: 8295095Abstract: Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial programming is verified by applying a ramped voltage having a first voltage range (e.g., where the first voltage range is selected in response to program coupling effects from memory cells adjacent to the target memory cell.) A programming operation following the partial programming operation is performed on one or more adjacent memory cells which is then followed by additional programming of the target memory cell to adjust the memory cell from the partially programmed state to the final programmed state. A ramped voltage having a second voltage range different from the first voltage range is utilized to verify the programming of the target memory cell to the final programmed state.Type: GrantFiled: April 20, 2010Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventor: Mason Jones
-
Patent number: 8274826Abstract: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.Type: GrantFiled: July 19, 2010Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Hashimoto, Noboru Shibata, Toshiki Hisada, Tsuneo Inaba
-
Patent number: 8264872Abstract: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.Type: GrantFiled: August 26, 2009Date of Patent: September 11, 2012Assignee: STMicroelectronics S.r.l.Inventors: Guido De Sandre, Marco Pasotti
-
Patent number: 8264896Abstract: An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column.Type: GrantFiled: July 31, 2008Date of Patent: September 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Bikas Maiti, Lawrence N. Herr, Rajesh R. Kini, Tam M. Tran