Abstract: Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

Abstract: A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a second internal voltage generator generating a second internal voltage in response to the external power supply voltage, the second internal voltage is larger in absolute value than the first internal voltage, and a preset signal generating circuit responding to a power-on of the external power supply voltage to the semiconductor apparatus and generating first and second preset signals which bring the first and second internal voltage generators into respective initial states, generation of the second preset signal is stopped after stopping generation of the first preset signal, in which the first internal voltage generator is released from its initial state in response to the stopping the generation of the first preset signal to be allowed to generate the first internal voltage, the second internal voltage generator is released from its initial state in

Abstract: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Abstract: Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor.

Abstract: A plurality of cell arrays are assigned different addresses. An access information unit holds access enable information indicating the number of the cell arrays to be simultaneously activated. An array control unit activates at least one of the cell arrays corresponding to the access enable information, in response to an access request, and forcibly activates at least one of the cell arrays not corresponding to the access enable information, in response to a forced access request. Consequently, it is possible to activate the inactivated cell array not corresponding to the access enable information before the supply of the access request. Therefore, even when the number of the cell arrays to be simultaneously activated is small, it is possible to execute access operations without interruption. As a result, it is possible to access the cell arrays with minimum power consumption without lowering access efficiency.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented.

Abstract: Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

Abstract: A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not.

Abstract: A circuit includes, in part, a multitude of magnetic random access memory cells, one or more column decoders, one or more row decoders, and a write driver circuit. The write driver circuit is responsive to data signal as well as to read/write signals. During writing of a first data to a selected magnetic random access memory cell, the write driver circuit causes the first signal line to be at a second voltage and the second signal line to be at the first voltage. The second voltage is greater than the first voltage. During writing of a second data to the selected magnetic random access memory cell, the write driver circuit cause the first signal line to be at a third voltage and the second signal line to be at the second voltage. The third voltage is smaller than the first voltage.

Abstract: Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.

Abstract: An information memory device using an electromagnetic-wave resonance phenomenon is provided to achieve both high density and long-period storage of stored data. Memory cells are three-dimensionally arranged in the inside of a solid-like medium which is not contacted with a surface of the medium, and the memory cell has resonance characteristics to electromagnetic waves depending on the space coordinates of the memory cell. For the medium, a material is selected so that an electromagnetic wave having the resonance frequency of the memory cell. By observing absorption spectra of the irradiated electromagnetic wave or emission spectra after the absorption, three-dimensional space coordinates of the memory cell are calculated.

Abstract: A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed above the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an appl

Abstract: In a surface emitting laser element, on a substrate whose normal direction of a principal surface is inclined, a resonator structural body including an active layer, and a lower semiconductor DBR and an upper semiconductor DBR sandwiching the resonator structural body are stacked. A shape of a current passing through region in an oxide confinement structure of the upper semiconductor DBR is symmetrical to an axis passing through a center of the current passing through region parallel to an X axis and symmetrical to an axis passing through the center of the current passing through region parallel to a Y axis, and a length of the current passing through region is greater in the Y axis direction than in the X axis direction. A thickness of an oxidized layer surrounding the current passing through region is greater in the ?Y direction than in the +X and ?X directions.

Abstract: A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the magnetic tunnel junction; the one field line is used for passing a field current for switching a magnetization of the storage layer of the magnetic tunnel junctions of the cells. A magnetic memory device can be formed by assembling an array of the memory units, wherein at least two adjacent magnetic tunnel junctions of the cells can be addressed simultaneously by the field line. The memory unit and magnetic memory device have a reduced surface area. Magnetic memory devices with an increased density of memory units can be fabricated resulting in lower die fabrication cost and lower power consumption.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented.

Abstract: An ejecting head ejects liquid material to a part to be ejected from a first nozzle during a first san period and from a second nozzle during a second scan period. A scanning unit relatively moves at least one of the ejecting head and a stage in the X-axis direction with respect to the other between the first scan period and the second scan period.

Abstract: An optical focusing system is configured to generate a data profile, wherein the data profile is configured to provide signals for operation of an actuator. Application of the signals from the data profile results in focus of optics within a label region of an optical disc. An image is printed on the label region of the optical disc while the optics focus on the label region of the optical disc by applying signals to the actuator according to the data profile.

Abstract: Systems and methods are provided for electronically adjusting an image to compensate for laser beam process direction position errors in an electrophotographic device. Initially, a bow profile is defined that characterizes the process direction position errors of a laser beam across a scan line. The device subsequently reads an image to be printed from a first memory location, performs pixel shifts on select columns thereof based upon the bow profile, and temporarily stores the adjusted image data to a second location of memory. The adjusted image data is then communicated to a printhead of the device.

Abstract: A supply chain monitoring system having a laser-based image system usable within an object processing facility to form images in objects, a reader operable to read the images on the objects, and an object tracking system coupled to the reader over a data network. The laser-based image system includes an image forming device operable to form an array of laser-treated regions in the objects in single shot events, where the arrays of laser-treated regions are associated with images.

Abstract: An image forming apparatus for forming images with an electrophotographic system. The image forming apparatus includes a laser drive unit configured to control a laser light, and an image data transfer control unit configured to control image data from to the laser drive unit. The apparatus also includes a polygon mirror configured to reflect laser light from the electrophotographic system, a polygon mirror drive unit including a motor configured to rotate the polygon mirror, and a power supply level detecting unit configured to detect a voltage level of power supplied to the polygon mirror drive unit by an electric power supply unit. The image data transfer control unit is configured to provide any width and any number of a first pulse signal indicating a state when power supply is cut off to the polygon mirror drive unit.