Patents Examined by Han V Doan
  • Patent number: 11934696
    Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 19, 2024
    Assignee: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Patent number: 11928361
    Abstract: In a memory system, a controller writes data of a plurality of clusters into a first memory area via a plurality of channels according to a write command regarding sequential data from a host. The controller specifies the order in which the data of the plurality of clusters is written according to log information and generates order information according to the specified order. The order information is information in which identification information of the cluster and information indicating a writing order are correlated with each other. The controller reads the data of the plurality of clusters from the first memory area according to a read instruction regarding an internal process and rearranges the read data of the plurality of clusters according to the order information. The controller writes the rearranged data of the plurality of clusters into the second memory area via the plurality of channels according to a write instruction regarding the internal process.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 12, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Taiki Wada
  • Patent number: 11907574
    Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Siciliani, Floriano Montemurro
  • Patent number: 11880598
    Abstract: Techniques for managing sequencing requests for storage node operations based on types of operations being sequenced. The techniques manage sequencing requests for different types of operations, such as backup and recovery operations, replication operations, migration operations, and so on, in a manner that avoids overwhelming storage node capacity. The techniques include receiving a sequencing request for an operation of a specified operation type at a request manager of a storage node and determining whether a capacity of the storage node is available for running the operation by a capacity manager for the specified operation type, in which the capacity manager is provided by a storage client and implemented on the storage node separate from the request manager. In this way, throttling, limiting, and/or prioritization requirements of the operation of the specified operation type can be defined by the storage client in a manner agnostic to the request manager.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: January 23, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Peerapat Luxsuwong, Sathya Krishna Murthy, Charles Christopher Bailey
  • Patent number: 11880570
    Abstract: A storage systems is configured so that when a network interface receives a write request, the network interface performs protocol processing on the write request and transfers a write command to a storage controller, the storage controller reserves a data storage area in a cache memory, the network interface receives a data transfer request from the storage controller and stores data relating to the write request in the reserved storage area of the cache memory, the storage controller transfers a write response to the network interface, and the network interface responds to the source of the write request.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 23, 2024
    Assignee: HITACHI, LTD.
    Inventor: Nobuhiro Yokoi
  • Patent number: 11782602
    Abstract: Systems and methods described herein provide for determining priority levels within one or more data streams established between a host computing device and a storage device. Data streams that have been assigned a sufficiently high priority may be provided additional processing resources available within the storage device. These additional processing resources may include an increased number of write buffers, superblocks, and access to other ancillary resources that facilitate an increased level of performance compared to data streams not provided additional processing resources. The assignment of priority to the data streams can occur through the use of one or more priority identifiers. Many types and scales of priority identifiers may be used. The establishing of this system of priority identifiers can occur by the storage device notifying the hose of the accepted priority identifier usage. In other embodiments, the storage device may come preconfigured with a priority indication system and scale.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ravishankar Surianarayanan
  • Patent number: 11775212
    Abstract: A data storage device includes a first memory device storing first data; a second memory device including a first zone storing second data, a second zone storing third data, and a third zone storing fourth data; a storage; and a controller in communication with the first memory device, the second memory device, and the storage and configured to receive one or more requests from a host and control an input and output of data from and to the first memory device, the second memory device, and the storage in response to the one or more requests from the host. The controller is further configured to copy a portion of the first data read from the first memory device to the first zone, copy a portion of the second data read from the first zone to the second zone, copy a portion of the third data read from the second zone to the third zone, and store data read more than a set number of times among data stored in the first memory device and the second memory device in the third zone.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 3, 2023
    Assignee: SK HYNIX INC.
    Inventor: Da Eun Song
  • Patent number: 11775442
    Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 3, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Monish Shantilal Shah, John Grant Bennett
  • Patent number: 11740793
    Abstract: A data storage system having non-volatile media, a buffer memory, a processing device, and a data pre-fetcher. The data pre-fetcher receives commands to be executed in the data storage system, provides the commands as input to a predictive model, obtains at least one command identified for pre-fetching, as output from the predictive model having the commands as input. Prior to the command being executed in the data storage device, the data pre-fetcher retrieves, from the non-volatile memory, at least a portion of data to be used in execution of the command; and stores the portion of data in the buffer memory. The retrieving and storing the portion of the data can be performed concurrently with the execution of many commands before the execution of the command, to reduce the latency impact of the command on other commands that are executed concurrently with the execution of the command.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Alex Frolikov, Zachary Andrew Pete Vogel, Joe Gil Mendes, Chandra Mouli Guda
  • Patent number: 11740812
    Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates with the storage device in accordance with a non-volatile memory host controller interface specification. The host provides a customized module containing instructions for performing the operations of a customized command. The host sends an idle time command to the storage device for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device executes the idle time command, during which the module may be used by the controller of the storage device.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11720261
    Abstract: Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Nadav Grosz, Jonathan S. Parry, Deping He
  • Patent number: 11669272
    Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, Steven S. Williams, Mark Ish
  • Patent number: 11625191
    Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Arash Hazeghi, Pranav Kalavade, Rohit Shenoy, Krishna Parat
  • Patent number: 11620080
    Abstract: A technique involves determining, in redundant array of independent disks (RAID) stripes, source slices for restriping, and allocating, from a reserved capacity for file system check (FSCK), destination slices for restriping. The technique further involves performing restriping for the RAID stripes by copying data in the source slices into the destination slices. Accordingly, using the reserved capacity for FSCK as the destination slices for restriping may mitigate the influence on an available capacity of a mapper during restriping, thereby improving the performance of a storage system.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 4, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Yousheng Liu, Xinlei Xu
  • Patent number: 11573738
    Abstract: A synchronous destage process is used to move data from shared global memory to back-end storage resources. The synchronous destage process is implemented using a client-server model between a data service layer (client) and back-end disk array of a storage system (server). The data service layer initiates a synchronous destage operation by requesting that the back-end disk array move data from one or more slots of global memory to back-end storage resources. The back-end disk array services the request and notifies the data service layer of the status of the destage operation, e.g. a destage success or destage failure. If the destage operation is a success, the data service layer updates metadata to identify the location of the data on back-end storage resources. If the destage operation is not successful, the data service layer re-initiates the destage process by issuing a subsequent destage request to the back-end disk array.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: February 7, 2023
    Assignee: Dell Products, L.P.
    Inventors: Lixin Pang, Rong Yu, Peng Wu, Shao Hu, Mohammed Asher Vt
  • Patent number: 11543999
    Abstract: A memory controller for controlling a memory device includes a host interface and a background controller. The host interface communicates with a host through a link, determines whether quality of the link has been degraded by monitoring the quality of the link, and performs a link recovery operation on the link when it is determined that the quality of the link is degraded. The background controller controls the memory device to perform a background operation, while the link recovery operation is being performed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventor: Rengaraja Sudarmani
  • Patent number: 11544001
    Abstract: A first storage node is connected to a host by using a first network interface card of the first storage node, and is connected to a second storage node by using a second network interface card. The first storage node receives a data processing request from the host, wherein the data processing request carries a target storage address of to-be-processed data, determines the second storage node based on the target storage address of the to-be-processed data, and sends the data processing request to the second storage node by using the second network interface card, wherein the data processing request instructs the second storage node to process the to-be-processed data.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 3, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianhua Zhou, Meng Zhou, Kun Tang
  • Patent number: 11507173
    Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Akihiro Kimura, Hiroki Matsushita
  • Patent number: 11403025
    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 2, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur John Redfern, Asheesh Bhadwaj
  • Patent number: 11397528
    Abstract: A snapshot for use in a cascaded snapshot environment includes a device level source sequence number and a Direct Image Lookup (DIL) data structure. The device level source sequence number indicates the level of the snapshot in the cascade, and the snapshot DIL indicates the location of the data within the snapshot cascade. A target device for use in the cascaded snapshot environment includes a device level target sequence number, a track level sequence data structure, and a DIL. When the target device is linked to a snapshot, the device level target sequence number is incremented, which invalidates all tracks of the target device. The snapshot DIL is copied to the target device, but a define process is not run on the target device such that the tracks of the target device remain undefined. IO operations use the device level target sequence number to identify data on the target device.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: July 26, 2022
    Assignee: Dell Products, L.P.
    Inventors: Sandeep Chandrashekhara, Michael Ferrari, Jeffrey Wilson