Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.

Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

Abstract: A snapshot for use in a cascaded snapshot environment includes a device level source sequence number and a Direct Image Lookup (DIL) data structure. The device level source sequence number indicates the level of the snapshot in the cascade, and the snapshot DIL indicates the location of the data within the snapshot cascade. A target device for use in the cascaded snapshot environment includes a device level target sequence number, a track level sequence data structure, and a DIL. When the target device is linked to a snapshot, the device level target sequence number is incremented, which invalidates all tracks of the target device. The snapshot DIL is copied to the target device, but a define process is not run on the target device such that the tracks of the target device remain undefined. IO operations use the device level target sequence number to identify data on the target device.

Abstract: A data processing system may include: a host suitable for including a first physical address corresponding to a first logical address in a first command, wherein the first physical address and the first logical address are associated with data, and sending the first command with the first physical address; and a memory system suitable for performing an operation corresponding to the first command by using the first physical address received from the host, and sending a result of the performed command operation to the host as a response, the host may check a time difference between a first time point that the first command is sent and a second time point that the response corresponding to the first command is received, and may determine whether to use the first physical address in a next command, based on a result of the time difference check.

Abstract: Methods and apparatus for managing and optimizing data storage devices that include non-volatile memory (NVM) are described. One such method involves deriving a hint for one or more logical block addresses (LBAs) of a storage device based on information received from a host device and/or physical characteristics of the storage device, such as LBAs that are invalidated together; grouping the LBAs into one or more clusters of LBAs based on the derived hint and a statistical analysis of the physical characteristics of the storage devices; allocating available physical block addresses (PBAs) in the storage device to one of the LBAs based on the one or more clusters of LBAs to achieve optimization of a data storage device.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A storage system and sorting-based method for random read command prediction in a multi-queue system are provided. In one embodiment, a method for command prediction is performed in a storage system comprising a memory and being in communication with a host. The method comprises receiving a read command sequence from the host, wherein read commands in the read command sequence originate from a plurality of command queues in the host such that read commands in the read command sequence received from the host are out of order; sorting read commands in the read command sequence received from the host based on logical block addresses; and predicting a next read command from the sorted read commands. Other embodiments are provided.

Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

Abstract: Methods and systems for storage services is provided. One method includes configuring by a processor, a database availability group (DAG) storing an active database copy at a first computing node and a passive database copy of the active database copy at a second computing node; initiating a backup operation for backing up the passive database copy from the second computing node; and interfacing with the first computing node by the second computing node for completing the backup operation. The first computing node identifies logs for the backup operation, backs up the identified logs and provides metadata associated with the backup of the identified logs to the second computing node. The second computing node updates metadata for the backup operation such that a backup copy of the passive database copy points to the second node with metadata received from the first computing node.

Abstract: A storage volume functioning at least in part as cache for a tiered storage system, the storage volume having an in-memory write extent consisting of write-accessed grains retrieved from a plurality of hot extents in a first tier of the tiered storage system, where the in-memory write extent is a same size as a block erase size of a solid-state drive tier of the tiered storage system. The storage volume further having an in-memory read extent consisting of read-accessed grains retrieved from the plurality of hot extents in the first tier of the tiered storage system.

Abstract: A memory system includes a memory controller, a first memory bank having a first I/O bus, a second memory bank having a second I/O bus, and a channel connecting the first I/O bus and the second I/O bus to the memory controller. The channel is used to transmit data between the first memory bank and the memory controller and between the second memory bank and memory controller, and is also used to transmit a command from the memory controller to the first memory bank and the second memory bank. The memory controller includes a bank command scheduler implemented in a hardware logic block. The hardware logic block includes a plurality of direct inputs and is able to determine, based on the plurality of inputs, an order in which to output commands to the first memory bank and the second memory bank over the channel; output a first command to the first memory bank; and output a second command to the second memory bank over the channel.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.

Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Abstract: A translation buffer is provided in parallel to a translation lookaside buffer (TLB) to cache translations between intermediate physical addresses (IPAs) and pointers for entries in the TLB corresponding to the IPAs. The pointers can be used to identify and invalidate only certain entries in the TLB as compared to invalidating the whole TLB.

Abstract: Offloading data storage to a decentralized storage network, including: identifying a plurality of decentralized storage networks that the storage system can utilize for storing data; selecting, in dependence upon characteristics of each decentralized storage network and requirements associated with storing the data, one or more decentralized storage networks for storing the data; and initiating storage of the data on the selected one of more decentralized storage networks.

Abstract: Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: collecting logging data generated by operation of a distributed computing system that is used by a plurality of tenants; storing the logging data as a plurality of files stored in a multi tier, shared volume storage system, with the storage of the logging data as a plurality of files including: dividing the plurality of files among and between a plurality of shared volume data structures, and organizing each shared volume data structure of the plurality of shared volume data structures according to a plurality of tiers; for each given file of the plurality of files; and mapping, by a domain agent and in a mapping table data structure, an association between the given file and the shared volume data structure in which the given file is stored.

Abstract: An apparatus monitors an access load state of a plurality of logical volumes of a first storage device, and determines that an access load state of a subset of the plurality of logical volumes has changed from a high load state to a low load state. The apparatus migrates, when the subset of the plurality of logical volumes remains in a low load state after an elapsed setting time since the load state of the subset of the plurality of logical volumes changed from a high load state to a low load state, data stored in the subset of the plurality of logical volumes to a second storage device having an access rate lower than the first storage device.

Abstract: An electronic device may include an information signal storage circuit and a write data selection circuit. The information signal storage circuit may be configured to store an information signal during a mode register set operation, and may be configured to output the stored information signal as a mode register information signal. The write data selection circuit may be configured to receive the mode register information and output the mode register information signal as write data.

Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

Abstract: A memory system is disclosed, which relates to technology for reducing overhead in a high-capacity memory device. The memory system includes a host and at least one memory. The host generates memory information by profiling history information about a memory access pattern. The memory device predicts a pattern of data to be accessed at a subsequently accessed page in response to the memory information, generates subset data according to the predicted data pattern, and transmits the generated subset data to the host. The subset data is less than all the data of the subsequently accessed page, which improves the speed and efficiency of the memory system.