Patents Examined by Han V Doan
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Patent number: 10503409Abstract: Embodiments described herein provide a system for facilitating a lightweight distributed storage system. During operation, the system generates a data segment from a data file associated with a write operation and determines a storage key for the data segment. The storage key indicates a calculated storage path associated with a replica of the data segment. The system then determines whether a user-defined storage path is specified by a user for the data segment. If a user-defined storage path has not been specified by the user for the data segment, the system generates a data packet comprising the data segment, wherein a destination for the data packet corresponds to a target disk specified by the calculated storage path.Type: GrantFiled: September 27, 2017Date of Patent: December 10, 2019Assignee: Alibaba Group Holding LimitedInventors: Shu Li, Ming Lin
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Patent number: 10452544Abstract: Embodiments are described for a multi-node file system, such as a clustered or distributed file system, with a file system buffer cache and an additional host-side tier non-volatile storage cache such as 3DXP storage. Cache coherency can be maintained by one of three models: (i) host-side tier management, (ii) file system management, or (iii) storage array management. performing a storage tier-specific file system action in a file system that comprises a namespace that spans multiple tiers of storage.Type: GrantFiled: September 27, 2017Date of Patent: October 22, 2019Assignee: EMC IP Holding Company LLCInventors: Stephen Smaldone, Ian Wigmore, Arieh Don
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Patent number: 10452543Abstract: Embodiments are described for a multi-node file system, such as a clustered or distributed file system, with a file system buffer cache and an additional host-side tier non-volatile storage cache such as 3DXP storage. Cache coherency can be maintained by one of three models: (i) host-side tier management, (ii) file system management, or (iii) storage array management. performing a storage tier-specific file system action in a file system that comprises a namespace that spans multiple tiers of storage.Type: GrantFiled: September 27, 2017Date of Patent: October 22, 2019Assignee: EMC IP Holding Company LLCInventors: Stephen Smaldone, Ian Wigmore, Arieh Don
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Patent number: 10430348Abstract: Provided are a computer program product, system, and method for selecting cache lists indicating tracks in a cache to process for demotion. In response to a selected cache list indicated as stalled as a result of a determination that there are less than a threshold number of unmodified tracks in the selected cache list, the selected cache list is indicated as not stalled in response to determining that the cache lists other than the selected cache list were indicated as not stalled since the selected cache list was last indicated as not stalled. The selected cache list is processed to determine whether there are unmodified tracks in response to indicating the selected cache list as not stalled. The determined unmodified tracks in the selected cache list are processed for demotion from the cache.Type: GrantFiled: June 14, 2016Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Lokesh M. Gupta
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Patent number: 10353612Abstract: According to one embodiment, a storage system includes a nonvolatile memory and a controller. The controller classifies blocks in the nonvolatile memory into a plurality of first blocks and a plurality of second blocks organized as a plurality of block groups each including a set of blocks. The controller receive a first read, write or erase command from a host, and performs a read, write or erase operation on one first block in the first blocks that is designated by a physical address of the first read, write or erase command. The controller receive a second read, write or erase command from the host, and performs a read, write or erase operation on blocks in one block group in the block groups that is designated by a physical address of the second read, write or erase command.Type: GrantFiled: August 29, 2016Date of Patent: July 16, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shinichi Kanno
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Patent number: 10353635Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.Type: GrantFiled: July 31, 2018Date of Patent: July 16, 2019Assignee: Pure Storage, Inc.Inventors: John Hayes, Par Botes
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Patent number: 10338844Abstract: A storage control apparatus including a memory that stores information that indicates an amount of data that have been written to a storage device, the storage device being coupled to a backup storage device for the storage device, and a processor coupled to the memory and the processor configured to determine an execution period of a verification process to verify a performance of the backup storage device based on the information stored in the memory and a total data capacity written to the storage device in a guarantee period of the storage device.Type: GrantFiled: August 29, 2016Date of Patent: July 2, 2019Assignee: FUJITSU LIMITEDInventor: Kazuyuki Sunaga
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Patent number: 10331550Abstract: This disclosure describes, in one embodiment an apparatus. The apparatus includes a processor; a memory, an application, collector circuitry and aggregator circuitry. The memory is to store one or more tasks. The application is associated with the one or more tasks. The collector circuitry is to identify a local free address range in at least one address space. The aggregator circuitry is to provide address range data to a subgroup aggregator. The provided address range data includes at least one local free address range.Type: GrantFiled: September 30, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: David Keppel, Charles J. Archer
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Patent number: 10296258Abstract: Offloading data storage to a decentralized storage network, including: identifying a plurality of decentralized storage networks that the storage system can utilize for storing data; selecting, in dependence upon characteristics of each decentralized storage network and requirements associated with storing the data, one or more decentralized storage networks for storing the data; and initiating storage of the data on the selected one of more decentralized storage networks.Type: GrantFiled: March 9, 2018Date of Patent: May 21, 2019Assignee: Pure Storage, Inc.Inventor: Michael Richardson
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Patent number: 10289329Abstract: A method, data processing system and program product utilize dynamic logical storage volume sizing for burst buffers or other local storage for computing nodes to optimize job stage in, execution and/or stage out.Type: GrantFiled: February 15, 2017Date of Patent: May 14, 2019Assignee: International Business Machines CorporationInventors: Thomas M. Gooding, David L. Hermsmeier, Jin Ma, Gary J. Mincher, Bryan S. Rosenburg
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Patent number: 10275162Abstract: Methods and systems that may be implemented for managing data migration from relatively higher performance and higher endurance solid state non-volatile memory media to relatively lower performance and lower endurance solid state non-volatile memory media. The disclosed methods and systems may be implemented to reduce write amplification that occurs to solid state non-volatile memory media of a memory device by using frequency of LBA update as a parameter for controlling and optimizing data eviction from a relatively higher performance and higher endurance input buffer section in the receiving front of a memory device to a relatively lower performance and lower endurance main memory section of the same memory device.Type: GrantFiled: June 23, 2017Date of Patent: April 30, 2019Assignee: Dell Products L.P.Inventors: Lip Vui Kan, Young Hwan Jang
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Patent number: 10254962Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.Type: GrantFiled: May 31, 2018Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
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Patent number: 10254968Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM module, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.Type: GrantFiled: May 10, 2016Date of Patent: April 9, 2019Assignee: FIRQUEST LLCInventors: Hillel Gazit, Sohail Syed, Gevorg Torjyan
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Patent number: 10223016Abstract: Example methods are provided to perform power management for a distributed storage system accessible by a cluster in a virtualized computing environment. The method may comprise determining that a power-off requirement is satisfied for a first host from the cluster. The power-off requirement may be satisfied based on multiple second hosts from the cluster complying with a data placement policy configured for the cluster after the first host is powered off. The method may also comprise based on the data placement policy, placing virtual machine data stored on the first host onto one or more of the multiple second hosts. The method may further comprise migrating one or more virtual machines supported by the first host to one or more of the multiple second hosts; and powering off the first host.Type: GrantFiled: May 10, 2016Date of Patent: March 5, 2019Assignee: VMWARE, INCInventors: Shi Chen, Pin Xie, Ting Yin
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Patent number: 10216428Abstract: A system for a storage controller configuration system of a storage server comprises an input interface and a storage controller request creator. The input interface is for receiving one or more commands to instantiate a set of virtual storage devices. The storage controller request creator for: 1) providing instantiation instructions for the set of virtual storage devices for storage in a cache and 2) in the event a request is received to create a mapping between a virtual storage device of the set of storage devices, a LUN, a port, and a client initiator: providing an instantiation indication to instantiate the set of virtual storage devices and providing a storing indication to store the mapping in a LUN table.Type: GrantFiled: March 27, 2015Date of Patent: February 26, 2019Assignee: EMC IP Holding Company LLCInventor: Shobhan K. Chinnam
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Patent number: 10204047Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.Type: GrantFiled: March 27, 2015Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Israel Diamand, Nir Misgav, Aravindh Anantaraman, Zvika Greenfield
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Patent number: 10168955Abstract: In an information processing device 10, a control unit 50 that performs a job of storing information on a recording medium selected from among a plurality of recording media or a job of reading the information from a recording medium on which desired information is stored among the plurality of recording media by controlling a recording media drive is arranged. The control unit 50 divides a plurality of the jobs into a group performing storage of the information and a group performing reading of the information and performs a setting process of setting an execution sequence of the jobs in order of the groups and, for the job of reading the information, performs a combination process combining jobs of which recording media of transmission sources or transmission destinations of the information are common.Type: GrantFiled: June 9, 2015Date of Patent: January 1, 2019Assignee: Sony CorporationInventors: Kyosuke Yoshida, Takahiro Araki
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Patent number: 10162749Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.Type: GrantFiled: August 29, 2016Date of Patent: December 25, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shinichi Kanno