Abstract: A semiconductor memory apparatus includes a memory cell unit and an internal voltage stabilization apparatus. The memory cell unit includes a row decoder, a column decoder, and a memory cell array. The internal voltage stabilization apparatus includes an operation termination determination unit configured to determine whether an operation of the semiconductor memory apparatus is terminated on the basis of an external input voltage and output an operation termination command, a termination voltage generation unit configured to generate a termination voltage having a preset voltage value on the basis of a determination result of operation termination by the operation termination determination unit, and a switch unit. The switch unit includes a plurality of switches that are turned in response to the operation termination command, and supplies the termination voltage, input from the termination voltage generation unit, to a plurality of internal nodes of the memory cell array.

Abstract: A method for operating a memory device includes: receiving a program command, a memory address, and a program data from a controller; performing a first temperature sensing operation for measuring an internal temperature to produce a first result of the first temperature sensing operation; performing a program operation on the program data based on the first result of the first temperature sensing operation; performing a second temperature sensing operation for measuring an internal temperature to produce a first result of the second temperature sensing operation; and performing a temperature comparison operation for deciding whether the program operation failed when a difference between the first result of the first temperature sensing operation and the first result of the second temperature sensing operation is greater than or equal to a threshold value.

Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.

Abstract: According to one embodiment, a semiconductor memory device includes: planes each including a memory cell array including memory cells; a comparator configured to, when suspending a write operation and executing a read operation, compare a first plane address corresponding to the write operation with a second plane address corresponding to the read operation; and a controller configured to suspend the write operation and execute the read operation. The controller is configured to, based on an output signal from the comparator, execute the first read operation when the first and second plane addresses match, and execute the second read operation when the first and second plane addresses differ.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: In example embodiments, a SOT magnetic memory and operation method are provided that utilize SOT driven domain wall motion to achieve subsequent switching without the need for an external assist magnetic field. The magnetic memory includes a magnetic tunnel junction having a reference layer, a tunnel barrier layer and a free layer, where the tunnel barrier layer is positioned between the reference layer and free layer. A spin-orbit torque layer is disposed adjacent to the free layer. A pair of pinning site are positioned at a longitudinal end of the free layer and each has an opposite magnetization direction from the other. The SOT layer is configured to exert SOT and switch a magnetization direction of the free layer via domain wall motion in a direction of current flow when an electric current is passed through a length of the SOT layer.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

Abstract: A memory device includes active circuitry configured to process a segment set that corresponds to a source data, wherein: the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.

Abstract: Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.

Abstract: The invention provides a write protection circuit, which is applied to a data storage device. The data storage device comprises a controller and a plurality of flash memories. The flash memories comprise a write protection pin. The write protection circuit comprises a fuse and a switch. When the switch is operated in a turned on state, the fuse is directly grounded via the switch and therefore is burned, and a signal on the write protection pin of the flash memories becomes a signal with a low-level state so that the flash memories of the data storage device will be permanently inhibited to be written.

Abstract: The present invention provides a data processing method and system for a 2R1W memory. The data processing method comprises: selecting 2n+1 SRAM2P memories with the same depth and width in accordance with a depth and a width of the 2R1W memory to construct a hardware architecture of the 2R1W memory, one of the plurality of SRAM2P memories being an auxiliary memory, and the rest of the SRAM2P memories being main memories; and when the data are written in and/or read from the 2R1W memory, associating data in the main memories and data in the auxiliary memory in accordance with a current pointer address of the data and performing an XOR operation on the associated data to complete data writing and reading. Only extra ½n of the memory area is required to construct the 2R1W memory based on a conventional SRAM unit.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.