Abstract: A method of interfacing peripheral digital information gathering devices with a computer includes the positioning of an interface module with each peripheral device and obtaining information therefrom in series of N-bit words. Thereafter each such series of words is stored in the interface modules. Thereafter, words in the interface modules to be disregarded are electronically masked, and the output of non-masked words are stored in a memory. The memory is provided with a not-empty indicator adapted to block further input from the peripheral when the memory has words in storage. Thereupon, communication of the non-disregarded memory words occurs to the computer. The method also includes the usage of parallel-to-serial converters within each interface module to thus enable parallel data generated by the peripheral to be received in memory as serial data.

Abstract: In a data processing system wherein a memory is comprised of an unknown plurality of memory blocks of a basic capacity, arranged in an unknown plurality of modules which have an unknown capacity multiple of the basic capacity, a method addresses the memory location which involves the selection of the module containing such locations by use of a directory having a plurality of addressable locations.

Abstract: A dual set of memory control circuit cards, one of which services a master processor and one of which serves a slave processor in a data communication Network Support Processor. Each memory control circuit card provides a local memory for each of said processors and further provides access logic circuitry for developing addresses to access an external shared memory means. Control flags and interrupt signals regulate any conflict in operation between the two memory control circuit card units when accessing the commonly shared memory.

Abstract: A separate lock bit array (LBA) is provided in combination with a translation lookaside buffer (TLB) in a data processing system such that the lock bits are stored in and accessed from the LBA. A segment register with a portion for an "S" bit is included and when S=1, a translation operation for the lock bits is performed in parallel with the TLB accessing by use and operation of the LBA. In such operation, when S=1, lower order virtual bits from a central processing unit (CPU) address register are applied to the LBA to select one of the rows of the LBA which consists of virtual address bits and lock bits. Segment identification bits from the segment register are combined with virtual bits from the CPU address register and are applied to first and second compare circuits. If there is a match in the first compare circuit with a first group of virtual bits from an LBA location, a first flag signal is generated and applied to a gate circuit to gate out a first associated group of lock bits from a first location.

Abstract: A microprocessor control system includes a bit/byte memory array to enhance the performance characteristics of a microprocessor. The bit/byte memory array selectively allows the microprocessor to manipulate individual bits in the memory thereby reducing both execution time and program size. In addition, the bit/byte memory array allows the microprocessor to address data bytes in the memory array to quickly enable the transferring of large amounts of data.

Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.

Abstract: A memory transfer unit is provided which permits replacing messages stored in a message display system with a different set of messages stored in the memory transfer unit. A circuit is provided for supplying power from the message display system to the memory transfer unit and for inhibiting operation of the memory transfer unit unless the power supply to it has a proper operating voltage level. Pulses produced in the message display system are counted to determine the sequential locations of data in the memory transfer unit to be transferred to the message display unit for substitution for data stored in the message display unit.

Abstract: A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of one of a set of microinstructions stored in a control store. The microinstructions have a data path control field, a condition/size field and a next address control field. A microinstruction logic control is responsive to the microinstructions, and a memory control unit that includes a data cache memory array operates asynchronously with respect to the data path unit, translating virtual memory addresses to access data from the data cache memory array or from the central memory unit.

Abstract: An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines.

Abstract: The disclosure is directed to a multiprocessor data processing system. The data processing system of the invention generally comprises a plurality of microprocessor units and an instruction memory device electrically storing a common set of instructions in a pre-ordered sequence, each of said instructions being stored in representative, digital, electrical signal form. A tapped delay line instruction bus system is provided to electrically interconnect the instruction memory with each of the microprocessor units. The tapped delay line instruction bus system includes a plurality of individual tap buses and electrical controls operable to apply the digital electrical signals for each of the instructions stored in the instruction memory device to each of the individual tap buses, one tap bus at a time, in a timed, time-skewed sequence.

Abstract: A data processor uses complex instructions and a sequence controller to cause first and second fields of such instructions to process data, respectively, by first and second ALUs, with a third field of such instructions containing address information for addressing locations in a data addressing unit, generating addresses for selecting such data from a data memory storage device.

Abstract: A technique for voice or other similar communication signal storage (such as recording) and forwarding (such as playback) enables simultaneous access to multiple users through use of first-in-first-out memories (FIFO), microprocessor-controlled to fill intermediate memory RAMs at irregular intervals and to transfer the contents thereof to main memory RAMs for ultimate segmented disc recording, with playback therefrom also microprocessor-controlled at irregular intervals to transfer back recorded data in block form through the main memory RAMs and appropriate intermediate memory RAMs and FIFO memories associated with an appropriate playback channel or user. The various data transfers are controlled to avoid delays in the played back messages, succeeding segments of data being transferred to intermediate memory RAMs by the time the transfer of the previous segment is complete, thereby insuring continuity of communication.

Abstract: In a digital computing system with a central processing unit (CPU) and random access memory (RAM), an improved data access limitation and protection subsystem protects data stored within predetermined boundaries of the RAM. An operation code detector detects a unique operation code stored in the RAM and fetched by the CPU, and puts out a signal when the unique operation code is detected. An address latch stores a high and a low digital boundary address put out by the CPU when the address latch is enabled by the signal from the operation code detector. An address comparator compares digital addresses subsequently put out by the CPU with the stored boundary addresses and puts out a signal as the result of the comparison. The address comparator signal controls a switch which enables or disables an address transformer and a bi-directional data transformer.

Abstract: Hardware for performing microcode branching in a pipeline central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit lines of microcode which are in the pipeline when a branch has been sensed. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupling loading and pushing to accommodate the two branching speeds. The microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Abstract: A system for the detection of programmable stop codes in a data exchange performed between the local memory of a microprocessor and the peripheral unit in a microprocessor assembly using direct access circuit to the local memory. This circuit divides the access to a common bus permitting data exchanges between a peripheral unit and the local memory. The system comprises a random access memory receiving the data on addressing inputs and receiving an address bit on a data input, a control circuit having outputs which are respectively connected to validation and writing control inputs of the random access memory. The control circuit repectively receives on inputs, signals coming from the microprocessor or the direct access circuit and which respectively relate to the writing or reading input-output operations as well as to the address decoding of the data.

Abstract: A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.

Abstract: A controller for controlling access to a plurality of records that can be accessed and changed by several independent processors comprises: a plurality of flip-flops corresponding in number to the plurality of records with each flip-flop representing a particular record; a circuit for receiving a programmable control word from any of the processors which identifies multiple records of which access is sought; a circuit for selecting in parallel and logically ANDing output signals from all of those flip-flops which correspond to the identified records; a circuit for sending a signal, if the ANDing operation yields a logical ONE, to the processor which sent the control word signaling that it may access and change the identified records; a circuit for setting in parallel via a single pulse all of those flip-flops which correspond to the identified records if the ANDing operation yields a logical ONE; and a circuit for storing the control word if the ANDing operation yields a logical ZERO.

Abstract: A security system for a postage meter includes two memories, one of which is an electronically programmable READ-ONLY memory having non-volatile storage, while the second memory is a shadow RAM which is a composite memory having a first section composed of a volatile RAM and a second section composed of non-volatile storage. During a power outage, a computer strobes the second memory to transfer data from the volatile section to the non-volatile section. Upon restoration of the power, a transfer circuit which includes a detector of the incoming power directs the transfer of at least a portion of the stored data in each of the memories to the computer for a comparison to determine if any data has been altered by the loss of power.

Abstract: For the purpose of connecting a plurality of independent processor units to a single port of a main memory, the processor units are connected in series over individual interface controls, whereby the interfaces are expanded in comparison to the port interface without the interface conditions for the port being changed. The interface controls operate in reciprocal dependency on one another so that the memory access request arising within the processor unit chain becomes effective in individual succession by way of a reciprocal inhibiting without address control, whereby variable connector controls in the interface lines determine the transmission path of both directions between the main memory and the respectively active processor depending upon status signals which, among other things, are influenced by interface signals. Termination of a write operation and clear down of a completed connection occurs by way of an internal interface line of the chain circuit.