Abstract: A computer-peripheral interface includes a latch to receive parallel data from a peripheral, such as a cash register, with a hardware mask to reject irrelevant data, a simple FIFO memory and a parallel-serial converter for transmission to a controlling computer. These devices are controlled by a combination of five one-shots for timing, and a D flip-flop and gates. The problem of controlling a variety of peripherals, such as cash registers, by a central computer without also incorporating microprocessors or equivalent complicated devices in each peripheral yet still providing sufficient data handling capacity is solved.

Abstract: In a highly flexible but economical mapping system and method, a different multidigit source code is assigned to each element in a first set of elements containing a subset of elements to be mapped. The digits of an assigned source code are grouped into at least two different groups. For each element to be mapped, a multidigit destination code is stored identifying each mapped element within a second set of elements to which it is to be mapped. Each digit of the destination code is stored in association with a state that is definable by a group of digits of the source code. Upon receipt of a source code, if it is detected as representing an element to be mapped, the stored destination code associated therewith is retrieved and substituted for the source code to effect the mapping.

Abstract: A method and associated apparatus are used for customizing a multi-section document inserter which uses a standard program which defines all the executable routines for the document inserter. The method comprises the steps of providing user inputs as to the desired configuration and operation of the multi-station document inserter, translating the user inputs into a specific data table for use with the standard program in the multi-station document inserter, and incorporating the specific data table into the multi-station document inserter for selecting the executable routines of the standard program to be used in order to provide a multi-station inserter which is customized to accomplished particular user requirements.

Abstract: A logic state analyzer monitors an ongoing succession of logic states occurring in a collection of n-many digital signals, and stores in a memory a set of logic states selected from the ongoing succession. A logic state is any one of the 2.sup.n -1 possible patterns the n-many digital signals may exhibit. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored logic states are overwritten as the newest logic states are stored. Various storage qualification criteria may be specified, in which case an individual logic state is not stored unless it meets those criteria. Upon recognition of a specified trigger condition in the succession of logic states the logic state analyzer stores an operator selectable number of additional logic states, after which the monitoring and storing of logic states ceases and the stored contents of the memory are displayed. The trigger condition may be the detection of a designated sequence of selected logic states.

Abstract: In a system comprising data-processing units, some of which are masters and others of which are slaves, all the units are connected to a common bus via interface circuits. Only the master units are capable of acquiring instantaneous control of the bus by means of a resource allocation device. By utilizing a set of three basic control signals carried by the bus, three distinct addressing modes can be established: master-to-master, master-to-slave, general master-broadcasting to all units in accordance with a number of chronologies and transmission modes. In an alternative embodiment, substitutions of addresses can be performed directly on the bus.

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line.

Abstract: A pipelined microprogrammed data processing system is provided having a three-stage pipelined architecture implemented so as to in effect provide for the execution of a plurality of microinstructions using three separate processors operating 120 degrees out of phase with one another and sharing the same physical hardware. Synchronized microinstruction tasking and dynamic resource allocation are also provided in the system to provide both multiprogramming and multiprocessing on a microinstruction level.

Abstract: A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn calls other microinstruction sequences for deriving pointers representing the location of the called procedure and of arguments from operands in the call instruction. As the call microcode obtains each argument pointer, it places the pointer on the stack. After it has obtained all of the argument pointers, it passes the pointer to the called procedure and a pointer to the argument pointers to a general call microinstruction sequence. That microinstruction sequence locates the called procedure, makes a new frame including the argument pointers, and saves the state necessary to resume execution of the call microinstruction sequence itself.

Abstract: The control program for a programmable controller is entered and edited through a program terminal which displays the control program symbolically as a ladder diagram. Comment instructions are entered into the control program and associated comment data is entered and stored. The comment data is subsequently displayed by the program terminal along with the ladder diagram rung containing the comment instruction.

Abstract: A control system is described for controlling the flow of multi-format, multi-bit macroinstructions for loading data into registers. The control system is adapted to: (A) control microprogram flow of instructions based on data within a floating point macroinstruction, (B) speed up macroinstruction flow as a function of data within various fields of the macroinstruction, and (C) speed up macroinstruction branches.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A transaction execution system is provided in which key initiated transaction requests at a terminal remote from and in communication with a host data processing system are processed at the terminal under the selective control of the host. Each active transaction key at the terminal keyboard is assigned one of three different states by a financial institution table. Transactions requested by keys having a data entry state are handled within the terminal and with the additional consumer entered data required to complete the transaction being requested by and received by the terminal using sets of messages previously stored in the terminal by the host data processing system. Transactions designated by an interactive key state take place within and involve interactive communication between both the terminal and the host, enabling the responses and other communications generated by the host in connection with a transaction for a particular customer to be customized.

Abstract: A digital computer executes a first instruction set in an interleaved fashion with second and third instruction sets, the latter two of which are executed at the same time. The first, second, and third instruction sets together represent an assignment statement of a high level programming language, such as ALGOL and COBOL, and by executing the first, second, and third instruction sets as recited above, a substantial improvement in the execution time of the corresponding assignment statement is attained. A second embodiment executes the first instruction set in an interleaved fashion with only the second instruction set to also achieve an improvement in execution time of the corresponding assignment statement.

Abstract: A single-chip microcomputer comprises a processor incorporating a computation process control unit and an operation execution unit. The microcomputer further comprises a memory unit, an interface, a buffer storage cell, and a unit to control exchange of information transmitted through a system line. All these units and the processor with its computation process control unit and operation excution unit are interconnected by a bidirectional bus. The processor also includes a buffer storage cell, a processor information exchange control unit, and an address comparator, which are all interconnected. The single-chip microcomputer further contains a bus arbiter and a system line arbiter which are connected to the unit to control exchange of information transmitted through the system line. Finally, the microcomputer includes a system line address comparator connected to the processor and buffer storage cell.

Abstract: Cyclic instrument control and data acquisition functions which are critically dependent upon synchrony are directed from a computer based system including a FIFO buffer adapted to feedback the most recently active word from its output register and re-store said word at a corresponding sequential position in the FIFO queue. To accommodate complex and interleaved control and data acquisition cycles, each FIFO word has a state portion for commanding external devices, a persistence portion for specifying the duration of a selected state active in the FIFO output buffer for a desired persistence interval, and a repetition portion for specifying the number of consecutive discrete repetitions of the currently active state-persistence datum at the output of the FIFO. Termination of the cyclic sequence is accomplished at the expiration of a preselected number of complete repetitions of the cyclic sequence.

Abstract: A logic state analyzer monitors an ongoing succession of states occurring in a collection of digital signals, and stores in a memory a set of states selected from the ongoing succession. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored states are overwritten as the newest states are stored. Various storage qualification criteria may be specified, in which case an individual state is not stored unless the state meets those criteria. Upon recognition of a specified trigger condition in the succession of states the logic state analyzer stores an operator selectable number of additional states. The trigger condition may be as simple as the occurrence of a single specified state or may be as complex as the satisfaction of a sequence of specified states. The resulting collectivity of states stored in the memory may be termed a captured trace.

Abstract: A microprocessor based mark-sense ballot card reading system has automatic mark detection threshold adjustment, automatic skew and card speed correction, and provision for simultaneous, accurate reading of both sides of a ballot card regardless of card input orientation. A multidispatch, miltipage real time control program is utilized to enable multiple event detection on each card side and asynchronous processing of such multiple events on a two-sided card. Positive document sensing and control are monitored by the microprocessor control system. A folded card path card transport mechanism with diverter stations operates under microprocessor control to determine card destination.

Abstract: The operating modes and parameters of a logic state analyzer are selected by user interaction with a menu displayed upon a CRT. At the highest level of control the user may specify which menu is of interest, should there be more than one. The selected menu is displayed and contains mode selection fields whose labels indicate the various modes that are presently selected. Different modes are selected by positioning a cursor to the associated selection field and then pressing a mode selection key. Each such activation causes the next mode in a sequence of modes, associated with that particular field, to be the selected mode of operation. A descriptive label or phase corresponding to the selected mode is displayed as part of the selection field containing the cursor.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: In a transceiver, a synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory (PROM), where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. In the swallow counting device, two latches receive divisor related information supplied by the PROM. When the sampled state of a single up counter reaches a first latched number, the prescaler changes the modulus. Synchronous counting then continues, without reprogramming new values. When the up counter reaches a second latched number, a predetermined frequency ratio has been achieved, and the counter is reset.