Abstract: An electronic postage meter system includes a postage meter in a secure housing enclosing only an electronic accounting system having registers and a printer. All control for the postage meter is effected by way of a connector on the housing for connecting a mailing machine or service unit to the postage meter. In operation, a sole input to the meter is by way of a keyboard of the mailing machine and a sole signal output is to the mailing machine, for example, to a display. The postage meter has a program to continuously read out its registers to the connector upon an initial application of power to the connector and a service unit which may be adapted solely to display such signals.

Abstract: In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

Abstract: In a system having a host processor connected through a storage control unit to a cache store and a plurality of disk devices, segments of data which have been written to, while resident in the cache store, are transferred to the disks at some later time. If an abnormal condition, such as a bad spot on the disk, prevents the transfer of a segment from the cache store to the disk, an indicator is set for that segment by the storage control unit to prevent further attempts to transfer the segment. A segment whose indicator is set remains in the cache store until the host processor issues an initialize or a reset segment command.

Abstract: A copy reproduction machine is subdivided into discrete operating modules and coupled together by a shared communication line over which operating messages from and to the modules are transmitted. Each module includes a receiver for intercepting and capturing messages bearing the module's address and a transmitter for transmitting messages from the module and addressed to other modules over the shared communication line.

Abstract: There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.

Abstract: A multistage data routing system for routing a plurality of data streams comprises a cube comprising a plurality of stages sequentially numbered n-1 through 0 and an extra stage n situated to proceed n-1 of the cube. Stages n through 0 comprise a plurality of data switching boxes. Each box includes a first input port, a second input port, a first output port, a second output port, and apparatus for selectively coupling the first input port to at least one of the output ports and the second input port to at least one of the output ports. Extra stage n and stage 0 include apparatus for selectively bypassing stage n or stage 0 or neither stage n nor stage 0. The system further comprises a plurality of links, each coupling a selected ouput port of a selected stage to a selected input port of the next adjacent downstream stage.

Abstract: The invention is a bidirectional transposition exchange sorter for performing two overlapped sort operations overlapped in time with input/output operations so as to consume zero time. The sorter operates on the basis of a stack of cells, each of which contains two item storage locations and a comparator. The cells are arranged in a sorter stack configuration with a shift register monitor for each cell and an extra shift register position at the top of the sorter stack and also at the bottom. The monitor carries an indication of the current transfer mode for the cell. Each sort is carried out as two semi-sorts, input and output, which semi-sorts are time overlapped with the input and output operations typical of sort operations in computers. A portion of the sort operation takes place during an input step, so as to result in a partial reconfiguration of an unordered sequence at the end of the input semi-sort.

Abstract: An address transformation system receives an input address and outputs in response thereto a data store address indicating an operable address location in an associated data store even if the received input address identifies a defective location in the associated data store. The address transformation system includes an address shuffler coupled to receive the input address and output a shuffled address and an address translator coupled to receive the received input address and the shuffled address and output the data store address in response thereto. Economic considerations dictate that the address translator be constructed in such a way that it is unable to accommodate all possible combinations of defective address locations in the associated data store by translating an address indicating a defective location to an address indicating an operable location.

Abstract: A data communications controller, for use intermediately between a data processor and a data communications link such as a modem driven land line, relieves the data processor of time-consuming supervisory and data preparation tasks, normally associated with the use of a data link, by means of a block loadable transmit queue, an automatic cyclic redundancy check generator, an automatic time fill generator and a parity generator, a block unloadable receive queue, an automatic character translator, an automatic character monitor and a received serial bit queue in conjunction with a byte synchronizing detector, the operation or non-operation of each of the above elements and, if operational, the manner of that operation, being selectable by commands from the data processor, the commands from the data processor being intermingled with but distinguishable from data to be sent over the data link.

Abstract: Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.

Abstract: A high speed processor for a digital modem which transmits and receives data over voice grade telephone lines, for performing logical addition and subtraction operations during encoding and decoding of data as phase shift keyed modulation. A quarter square multiplying circuit is provided which executes multiplying operations at high speed. A discrete-input multiplexer is provided and controlled to bring single-bit variables into the processor as word variables permitting logic operations to be performed rapidly and efficiently. A bitwise logic circuit is provided in conjunction with the multiplexer and the processor to perform logic operations on bit pairs within the same word or on pairs of bits from different locations in two different operands. An interrupt subsystem includes a toggle circuit which alternately monitors for transmit and receive interrupts.

Abstract: A logic system maintains current least recently used information among the elements of each group in a plurality of groups where each group includes two or more elements. A memory stores intermediate information regarding the relative precedence between each combination of elements in a given group. A logic network recomputes this value each time an element in a group is used and provides this new information to the memory and to a network which resolves the current least recently used status.

Abstract: A measuring apparatus for measuring the time of execution of instructions or the number of cycles that addresses are within a selected address range of a memory. The measurement includes a measurement of any common subroutines that have been called by the instructions within the selected range. The measuring apparatus includes range circuitry connected to the address bus of the memory that detects instruction addresses within the selected range and instruction addresses within a common range having the common subroutines. The measuring apparatus further includes link logic for controlling a counter to both measure the instructions within the selected range and measure instructions within the common range when they immediately follow the selected range on the address bus. In the preferred embodiment, the memory is organized in ranges so that the first range begins at the first memory location in the memory and the last range ends at the last memory location in the memory.

Abstract: A communication network (10) has a memory unit (20) accessable to all ports (16-0, 16-1, 16-2, 16-3) of the link with a plurality of local sections (62) each associated with one of the ports. Interconnections include a dual memory bus (28) with a common bus subsystem (36) providing access to a common memory section and a local bus subsystem (30) providing access to the local memory sections, the subsystems constructed to permit concurrent independent use. Memory access priority circuitry (68) designates for each memory operating cycle a port for current service and makes memory access available to other elements when not required by the designated port.

Abstract: A computer control system for a controlled apparatus such as an elevator executes operation with a plurality of standard programs corresponding to the conventional standard elevator relay circuits, the plurality of standard programs being stored in a ROM (Read Only Memory) device.The computer control system is equipped with a special program corresponding to at least one of the plurality of standard programs, and the special program is stored in a ROM device. If the elevator is to operate in a standard mode, the computer control system operates using only the standard ROM devices. If the elevator is to operate in a modified mode, the computer control system operates using the standard ROMs together with the special ROM, a control signal corresponding to this special ROM device being employed as a valid control signal. In both modes of operation, the standard program is not modified.

Abstract: A DMA bus load varying unit applied to a data processing system has a DMA bus and a memory connected to the DMA bus is provided with a mode designating circuit for designating a memory read and write operation, a continuous operation of the memory read and write operation, and a start and stop operation of the memory read and write operation for the memory, a clock-pulse generator connected to said mode-designating circuit, a period counter connected to the clock-pulse generator for counting clock-pulse signals from the clock-pulse generator, a period-setting circuit for specifying an arbitrary period, a first comparator for comparing the output from the period counter with the output from the period-setting circuit and for producing a first coincident signal when they are equal, a flip-flop connected to the first comparator for producing the DMA bus request signal in accordance with the coincident signal; DMA bus circuit connected to the mode-designating circuit and the flip-flop which is triggered by the DM

Abstract: A computer system utilizing an N bit word in which a directly addressable space is limited to 2.sup.N-1 words or 2.sup.N characters by the system architecture. Extension of this directly addressable space to 2.sup.N words is accomplished by a combination of a memory management circuit and a character selection signal instructions which allows both characters and words to be mixed in a first 2.sup.N-1 words of directly addressable space and words only to be addressed in a second 2.sup.N-1 words of directly addressable space.

Abstract: A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

Abstract: A method for assuring atomicity of user requested multi-row update operations to tables such as in a relational database, guarantees that for any update operation that succeeds all stated effects will have occurred and that for any update operation that fails the system state as perceived by the user remains unchanged. This is accomplished by establishing, in response to a multi-row update operation request, an execution module of a program containing sets of machine language code instructions implementing the update operation request with a savepoint request at the beginning of the execution module of the program. For each set of machine language code instructions in or called by the execution module which modified the user perceived system state, information is logged to a soft log.

Abstract: A high volume mailing installation is disclosed in which the output of a programmable high speed electronic digital computer provides destination and postage amount information, a high speed chain printer driven by the computer prints the destination information on address labels, and an authorized postage printing meter is mounted piggy-back fashion on the chain printer and responds to the same computer for automatic printing of authorized postage impressions of the calculated amount on the same mailing labels. The meter includes a fast, rugged solenoid-actuated segmented flat bed postage printer unit and fixed-program electronic digital postal accounting circuitry, with appropriate security features to prevent or detect postal fraud.