Abstract: An interface apparatus, which interfaces a communication device to a highway wherein the highway includes a clock line, a data line, and a busy line, comprises a counter element which counts a clock signal transmitted on the clock line to generate a clock value. The counter includes a second input terminal connected to the busy line to disable the counting when a busy signal is present on the busy line. A compare element compares the clock value to a device number value associated with the communication device, each communication device coupled to the highway having a unique device number value, and outputs an enable signal when the clock value and the device number value are equal. A driver element permits data to be transmitted onto the data line in response to the enable signal when the communication device has data to be transmitted.

Abstract: An improved memory management system is described having particular application for use in computer systems employing virtual memory techniques. The system includes a CPU and other data processing devices, such as I/O devices, direct memory access (DMA) units, a system bus, etc., which are coupled to a "virtual" address bus for transferring virtual address information to a main memory unit (MMU). Access to the virtual bus is controlled by arbitration unit in order to insure that only a single device may communicate with the MMU at a time. In a preferred embodiment, address space within the MMU is allocated into a plurality of memory spaces, each space including translation data for use by a particular data processing device coupled to the virtual bus. A device gaining access to the virtual bus identifies the particular MMU memory space to be used for its address translation by providing unique context bits denoting the memory space to the MMU.

Abstract: A circuit detects that a plurality of signals are generated in a predetermined sequence. The plurality of signals are applied to address terminals of a memory which has stored therein a predetermined pattern, and a divide-by-N counter (N:positive integer) counts a first data output signal from the memory N times and applies a carry output signal generated as a result thereof to another address terminal of the memory. An output signal of the circuit is derived from a second data output terminal of said memory when the plurality of input signals occur in the predetermined pattern of the memory and the carry signal from the counter is applied to the memory.

Abstract: A programmable calculator utilizes an initialization key for setting all program variables, including array variables that are stored as part of a program in the calculator memory, to a predetermined initial value.

Abstract: A word processing system having foreground and background modes of operation, wherein the full capability of the word processing system is available to both the foreground mode and background mode. The system comprises a display, a processor system for processing information and controlling the display and having foreground/background capability so that two jobs may run concurrently, a first buffer for storing information relating to a first job being run in the foreground mode, a second buffer for storing information relating to a second job being run in the background mode, and an input device for entering textual and command information into the system. Information in the first buffer is displayed on the display.

Abstract: A multiprocessor system intercouples the processors with an active logic network having a plurality of priority determining nodes. Messages applied concurrently to the network in groups are sorted, using the data content of the messages, to a single or common priority message which is distributed to all the processors with a predetermined total network delay time. Losing messages are again retried concurrently in groups at a later time. Message routing is determined by local acceptance or rejection of messages at the processors, based upon destination data in the messages. All messages occupy places in a coherent priority scheme and are transferred in contending groups with prioritization on the network. Using data, status, control and response messages, and different multiprocessor modes, the system is particularly suited for configuration in a relational data base machine having capability for maintaining an extended data base and handling complex queries.

Abstract: A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.

Abstract: A peripheral unit controller loads a microprocessor program received from a host processor into a random access memory of a microprocessor-controlled peripheral unit. The program-controlled microprocessor included in the peripheral unit controls the transfer of data between the host processor and the memory and between the memory and a communication channel data link. The peripheral unit controller includes input and output buffer registers, a direct memory access controller, and a host access buffer. Connected between data and address buses of the peripheral unit, the host access buffer transfers controller addresses received from the host processor on the data bus to the address bus to load a program memory address and program word count into the registers of the direct memory access controller.

Abstract: Data modification and display apparatus for use in a digital computer system together with a method employing data modification and display apparatus for modifying and displaying data. The data modification and display apparatus has a memory containing buffer sections for storing data codes representing data to be modified, control data including a state value for controlling modification and display of data, an editing table containing editing instruction sequences for modifying the contents of the buffer, modifying the control data, and producing display codes, a terminal with a keyboard for providing input codes and a screen for displaying visual representations in response to display codes, and a processor. Editing instruction sequences are divided into sections corresponding to certain state values and editing instructions include instructions to which the processor responds by altering state value.

Abstract: Interface apparatus allows a serial communicating device to communicate with an echoplex communicating device. A first microprocessor coupled to the serial device converts serial data to a parallel format. The parallel formatted data is transferred to a second microprocessor which is coupled to the echoplex device. The second microprocessor converts the parallel data from the first microprocessor into echoplex data for transmission to the echoplex device. When data is to be transferred from the echoplex device to the first device, the second microprocessor converts the echoplex data to a parallel format. The parallel formatted data is transferred to the first microprocessor, for conversion into a serial form and transmission to the serial device. If both the serial and echoplex devices wish to transmit at the same time, priority is awarded to the echoplex device. The interface operates asynchronously on real time basis, and is transparent.

Abstract: An electronic document distribution network is provided having a uniform data stream which may be used by data processors of varying levels of data processing capability interconnected in the network. The network comprises a plurality of linked communicating data processors. Each of the processors has apparatus for receiving and for transmitting a uniform data stream which is representative of the content and format of the document as well as the processing to be performed with respect to the document. The network includes higher level processors which have a higher level of data processing capability with respect to the data stream and lower level processors. One or more of the lower level processors further include apparatus for scanning a received data stream and for selecting from the data stream parameters which this lower level processor is capable of processing. The lower level processor also has apparatus for storing the non-selective parameters which it is not capable of processing.

Abstract: A video conversational data communication network (30) in which subscribers (34, 36) may conduct conversational video textual data communications with one or more keystations (70, 602, 98) in the network (30). Each keystation (70, 602, 98) is associated with a keystation terminal controller interface (68, 96, 600) which is in turn connected to a message switching node (32) for routing calls throughout the network (30). The keystation controller interface (68, 96, 600) locally stores (304, 306) video conversational textual data for its associated keystations (70, 82, 84, 98, 100, 602) and enables two different designated keystations to conduct two different video conversations with a common keystation in a split screen display (76). The split screen display (76) may also be used to display retrievable data from a data base (50, 52) for simultaneous display (76) along with a video conversation.

Abstract: A text comparator which includes a decoded data memory (13) which contains a plurality of shift registers (SR2.0.-SR7F), one shift register for each one of the plurality of different symbols forming the data base stored within the mass storage device (11). The decoded signal is applied to the input lead of the shift register associated with that character, and a clock signal applied to each shift register of the decoded data memory. In this manner, the decoded data memory will provide signals on the output leads of each shift register indicative of the most recently received character, as well as each of the preceding K characters received from the mass storage device and decoded, where K is the number of bits contained in each shift register of the decoded data memory.

Abstract: A method and apparatus is disclosed for independently displaying one of a plurality of images on a display and for superimposing the plurality of images onto one another to produce a composite image. One or more bit planes are selected to constitute a group (defined to be a "surface"), and one or more additional bit planes are selected to constitute another group. The number of groups corresponds to the number of images to be independently displayed. The priority of one group over the other is selected. This ensures that the image from the one group (surface) appears to be "in front of" the images from the other group (surface) on the display. In the case of a color terminal, the colors associated with each group are selected. A color map memory contains a plurality of brightness indices which determines image brightness. Associated with each index is one or more color indices.

Abstract: A method and apparatus for accessing a particular location in a main memory of a computer in which virtual addresses from a CPU are separated into direct and indirect address segments. The direct address segment is applied directly to one of row and column control lines that identify such location in the memory and the indirect address segment is translated into a real address segment and applied to the other of the row and column control lines of the main memory that identify the particular memory location. The row and column control lines are strobed with sequential pulses such that the control line to which the direct address segment is applied is strobed prior to the control line to which the translated real address segment is applied.

Abstract: A direct buffer access circuit provides a buffer memory for use with a host central processing unit and a peripheral controller for controlling an external data storage device such as a disk or tape drive. The buffer is connected so that both the host and the controller have direct access to the buffer. The host can thus transfer data to the buffer at its own data rate independently of the transfer rate of the controller. The buffer may include either a random access memory which is addressed by a counter, or a first-in/first-out memory. The buffer is controlled by signals received from either the host or the controller.

Abstract: The present invention is an emulator device for emulation of the functions and operation of a predetermined semiconductor device. A central portion of a semiconductor substrate of the emulator embodies the emulated semiconductor device. This embodiment of the emulated semiconductor device is an exact replica of the emulated device including all input and output connections. The emulator device further includes an additional set of input/output connections located on the periphery of the substrate outside the central portion. These additional input/output connections are connected to portions of the emulated device in the central portion of the substrate. These connections permit additional input signals to be coupled to the emulated device and additional output signals to be received from the device to enable greater control over and monitoring of the emulated device. This periphery preferably also includes further circuits for use in the emulator device for signal conditioning and the like.

Abstract: A video conversational data communication network (30) in which subscribers (34, 36) may conduct conversational video textual data communications with one or more keystations (70, 602,98) in the network (30). Each keystation (70, 602, 98) is associated with a keystation terminal controller interface (68, 96, 600) which is in turn connected to a message switching node (32) for routing calls throughout the network (30). The controller (68, 96, 600) locally stores (304, 306) video conversational textual data for its associated keystations (70, 82, 84, 98, 100, 602) and enables two different designated keystations to conduct two different video conversations with a common keystation in a split screen display (76). The split screen display (76) may also be used to display retrievable data from a data base (50, 52) for simultaneous display (76) along with a video conversation.

Abstract: A method .[.for.]. independently electronically .[.collecting.]. .Iadd.collects .Iaddend.related market survey data from a plurality of diverse locations (6,6') for temporary storage at each of the independent diverse locations (6,6') where the data is collected for subsequent transmission thereof from these locations (6,6') over a telephone type link (30,36,42) for accumulative processing thereof at a remote central electronic data processor. An interactive interchangeable prompt message display is displayed on a visual display device (32) indicating one of a plurality of market survey categories in a predefined sequence. An actual data input signal may be provided via a keyboard (70) or barboard (29) and/or wand (18,28) in response to the prompt message display with this input being stored in a memory (16) for subsequent transmission.

Abstract: A digital computing system having an auto-incrementing memory subsystem includes one or more separate memories. Each memory in the memory subsystem has its own address counter which is automatically incremented to the next sequential address after each memory readout. In the case of plural memories, a page select enables memory readout only when a page designation portion of the address matches a unique page number associated with the memory. An automatic memory refresh is provided by a refresh address counter along with a refresh address incrementer in the case that a memory is a dynamic RAM. These features enable improved performance in the digital computing system by reducing the required CPU overhead for memory subsystem control.