Patents Examined by Hashem Farrokh
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Patent number: 11281398Abstract: A data storage system including a frame, storage drives and a pair of stacked storage controllers. The system also includes a plurality of midplanes each having a PCB with opposing side surfaces, a front edge, a rear edge and a plurality of electrical traces. Each midplane further includes a first midplane connector coupled to the front edge, a second midplane connector coupled to the rear edge and a third midplane connector coupled to the rear edge, where the first connector is coupled to drive connectors and some of the electrical traces, the second connector is coupled to a controller connector and some of the electrical traces and the third connector is coupled to another one of the controller connectors and some of the electrical traces so that the midplanes are vertically oriented in parallel to define spaces therebetween relative to a front to rear direction of the frame.Type: GrantFiled: November 11, 2020Date of Patent: March 22, 2022Assignee: JABIL INC.Inventor: Fengquan Zheng
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Patent number: 11281387Abstract: A method, system, and computer program product for multi-generational virtual block compaction comprising identifying a first virtual block, the first virtual block being associated with a first generation number, determining a second virtual block as an appropriate target for live information in the first virtual block, creating an association between the second virtual block and the first virtual block, updating the live information in the first virtual block to be associated with the second virtual block, updating a generation information mapping associated with the first virtual block; and associating a second generation number with the first virtual block.Type: GrantFiled: July 1, 2019Date of Patent: March 22, 2022Assignee: EMC IP Holding Company LLCInventors: Ashok Tamilarasan, Vamsi Vankamamidi, Philippe Armangau
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Patent number: 11275507Abstract: A method, an electronic device, and a computer-readable storage medium for information processing are provided according to example embodiments of the present disclosure. The method comprises receiving, at a storage device, a data block and fingerprint information correlated with the data block, the fingerprint information being configured to identify the data block; and determining a storage position of the received data block based on predetermined correlations between fingerprint information and storage positions and the received fingerprint information, the predetermined correlations comprising at least correlations between historical fingerprint information correlated with stored data blocks and historical storage positions. Thus, a storage position of a data block can be determined based on received fingerprint information and predetermined correlations between fingerprint information and storage positions, thereby improving efficiency of redundant data deletion.Type: GrantFiled: May 15, 2020Date of Patent: March 15, 2022Assignee: EMC IP Holding Company LLCInventors: Chenxi Hu, Shixu Dong
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Patent number: 11275686Abstract: In one embodiment, a microprocessor, comprising: prediction logic comprising a branch predictor comprising a group of multi-set associative tables, each of the tables corresponding to branch pattern histories of different lengths; and control logic configured to provide an adjustable write policy for the prediction logic.Type: GrantFiled: November 9, 2020Date of Patent: March 15, 2022Assignee: CENTAUR TECHNOLOGY, INC.Inventor: Thomas C. McDonald
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Patent number: 11275682Abstract: A memory system includes a memory device comprising a memory block having a plurality of pages; and a controller suitable for receiving from an external device an erase request for an erase operation and a first logical address relating to the erase request, and correlating the first logical address to erase information.Type: GrantFiled: December 23, 2019Date of Patent: March 15, 2022Assignee: SK hynix Inc.Inventor: Byung-Jun Kim
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Patent number: 11249651Abstract: A storage system includes: a storage device to store an array of data elements associated with a sort operation; a storage interface to facilitate communications between the storage device and a host computer; and a reconfigurable processing device communicably connected to the storage device, the reconfigurable processing device including: memory to store input data read from the storage device, the input data corresponding to the array of data elements stored in the storage device; and a kernel including one or more compute components to execute the sort operation on the input data stored in the memory according to a SORT command received from the host computer. The reconfigurable processing device is to dynamically instantiate the one or more compute components to accelerate the sort operation.Type: GrantFiled: March 17, 2020Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sahand Salamat, Hui Zhang, Joo Hwan Lee, Yang Seok Ki
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Patent number: 11243719Abstract: According to one embodiment, a storage device includes a non-volatile memory, an interface circuit, a first control circuit, a wireless transmitting and receiving circuit, and a second control circuit. The interface circuit is electrically connected to the host device and is capable of communicating the host device. The first control circuit performs control of writing write data received from the host device via the interface circuit into the non-volatile memory. The wireless transmitting and receiving circuit is capable of wirelessly communicating with a wireless device. The second control circuit determines whether or not the write data include a predetermined type of data based on measurement data of the write data, and stops wireless communication performed by the wireless transmitting and receiving circuit if it is determined that the write data include the predetermined type of data.Type: GrantFiled: September 6, 2019Date of Patent: February 8, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kuniaki Ito
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Patent number: 11237729Abstract: An inversion encoder is configured to receive a plurality of bytes of data for parallel output to a data bus; determine, in parallel, Hamming distances of neighboring pairs of bytes of the received plurality of bytes of data; for each neighboring pair of bytes of the received plurality of bytes, determine, in parallel, for each of the neighboring pairs of bytes, whether a respective Hamming distance satisfies a majority function; if a respective Hamming distance for a particular pair of bytes of the neighboring pairs of bytes satisfies the majority function: set an inversion bit for a second byte of the particular pair of bytes to be the opposite of an inversion bit for a first byte of the particular pair of bytes; invert, or forgo inverting, the second byte based on the inversion bit for the second byte; and provide the second byte for output to the data bus.Type: GrantFiled: October 13, 2020Date of Patent: February 1, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Debasish Dwibedy, A Harihara Sravan, Nihal Singla, Muralikrishna Balaga
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Patent number: 11232054Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.Type: GrantFiled: May 24, 2021Date of Patent: January 25, 2022Assignee: NETLIST, INC.Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
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Patent number: 11232036Abstract: Writes to one or more physical storage devices may be blocked after a certain storage consumption threshold (WBT) for each physical storage device. A WBT for certain designated physical storage devices may be applied in addition to, or as an alternative to, determining and applying a user-defined background task mode threshold (UBTT) for certain designated physical storage devices. In some embodiments, the WBT and UBTT for a physical storage device designated for spontaneous de-staging may be a same threshold value. Write blocking management may include, for each designated physical storage device, blocking any writes to the designated physical storage device after a WBT for the designated physical storage device has been reached, and restoring (e.g., unblocking) writes to the designated physical storage device after storage consumption on the physical storage device has been reduced to a storage consumption threshold (WRT) lower than the WBT.Type: GrantFiled: August 2, 2019Date of Patent: January 25, 2022Assignee: EMC IP Holding Company LLCInventors: Gabriel Benhanokh, Andrew L. Chanler, Arieh Don
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Patent number: 11221790Abstract: A plurality of storage drives, for managing data. includes: transmitting a first data update command which specifies a first address, and first new data to a first storage drive included in the plurality of storage drives; updating a sequence number of the first address managed in the first storage drive in response to the first data update command; transmitting a first redundant data update command which specifies a second address of old redundant data, data for updating the old redundant data, and the updated sequence number, to a second storage drive which stores the old redundant data associated with the first address and which is included in the plurality of storage drives; updating the old redundant data based on the data for updating the old redundant data; and updating a sequence number of the second address managed in the second storage drive according to the updated sequence number.Type: GrantFiled: May 24, 2017Date of Patent: January 11, 2022Assignee: HITACHI LTD.Inventor: Tomohiro Yoshihara
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Patent number: 11221792Abstract: A storage system is configured to facilitate memory operations with the memory that avoid the need for defragmentation. The system includes one or more memory devices and a memory interface operatively coupled with the one or more memory devices. The memory interface includes a start page module that provides a start page table having a page number that includes a first part of a corresponding dataset. A link page module of the memory interface provides a link page table that indicates an address for a current page of a given dataset and an address for a next page of the given dataset. Write/read page modules of the memory interface provide write/read page tables that include sub-addresses of a page where a portion of a corresponding dataset is being written/read. The memory interface executes data read, write, and erase operations that are tracked using the tables provided by the various modules.Type: GrantFiled: October 13, 2020Date of Patent: January 11, 2022Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Michael A. Zalucki
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Patent number: 11216188Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.Type: GrantFiled: September 14, 2020Date of Patent: January 4, 2022Assignee: Kioxia CorporationInventors: Naoki Esaka, Shinichi Kanno
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Patent number: 11210022Abstract: Techniques involve: determining processing power of a plurality of storage devices in a plurality of storage pools, the storage devices in each of the storage pools having a same device type; dividing the plurality of storage devices into a plurality of sets based on the processing power, a difference in the processing power between the storage devices in each of the sets being below a predetermined threshold; and redistributing, among the plurality of sets, data stored in the plurality of storage devices based on workloads of the storage devices in the sets. Accordingly, load balancing of storage devices in the plurality of storage pools can be implemented, response speed of the storage system can be enhanced and storage resources in the plurality of storage pools can be exploited more sufficiently.Type: GrantFiled: September 25, 2019Date of Patent: December 28, 2021Assignee: EMC IP Holding Company LLCInventors: Chun Ma, Shaoqin Gong, Geng Han, Jian Gao, Xinlei Xu
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Patent number: 11204870Abstract: Techniques for cache management may include: receiving pages of data having page scores, wherein each of the pages of data is associated with a corresponding one of the page scores, wherein the corresponding page score associated with a page of data is determined in accordance with one or more criteria including one or more of a deduplication score, a compression score, and a neighbor score that uses a popularity metric based on deduplication related criteria of neighboring pages of data; and storing the page of data in a cache in accordance with the plurality of page scores. The cache may include buckets of pages where each bucket is associated with a different page size and all pages in the bucket are the different page size. The one or more criteria may also include an access score. The page scores may be based on multiple criteria that is weighted.Type: GrantFiled: March 13, 2020Date of Patent: December 21, 2021Assignee: EMC IP Holding Company LLCInventors: Anton Kucherov, David Meiri
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Patent number: 11204702Abstract: A host system executing multiple virtual machines that is associated with multiple storage domains may be identified. Storage domain data may be received that includes utilization of each of the multiple storage domains by the multiple virtual machines. It may be determined that the utilization of a first storage domain of the multiple storage domains by the virtual machines satisfies a threshold utilization. In response to determining that the utilization of the first storage domain satisfies the threshold utilization, a second storage domain may be identified in view of a storage domain rank. An instruction may be provided to cause a storage migration of a virtual machine from the first storage domain to the identified second storage domain.Type: GrantFiled: August 15, 2017Date of Patent: December 21, 2021Assignee: Red Hat Israel, Ltd.Inventors: Michael Kolesnik, Mordechay Asayag
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Patent number: 11194491Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: GrantFiled: November 14, 2019Date of Patent: December 7, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki
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Patent number: 11175846Abstract: A system and method for data co-location in hierarchical storage management (HSM) system are presented. Related data units may be grouped to be collectively accessed from a plurality of data units stored on a first sequential media. The related data units may be migrated from the first sequential media in the HSM system to a second sequential media in the HSM system to sequential and continuous access to the related data units on the second sequential media.Type: GrantFiled: April 11, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hiroyuki Miyoshi, Hiroshi Araki, Takeshi Ishimoto
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Patent number: 11163460Abstract: The present disclosure provides several embodiments of a dynamically-reconfigurable storage device. A primary feature of a dynamically-reconfigurable storage device is that it appears to a data store accessing device, such as a PC, as if it were an actual data store, say a USB thumb drive, whereas in reality the dynamically-reconfigurable storage device hosts several virtual data stores, each of which may be dynamically selectable to be made individually visible to the connected data store accessing device each as a separate actual data store. As such, a single dynamically-reconfigurable storage device is configurable to store what may appear, for example, as several individual USB thumb drives whereas said dynamically-reconfigurable storage device uses a single SD card to store all those virtual USB thumb drives.Type: GrantFiled: June 7, 2019Date of Patent: November 2, 2021Inventor: Karim Jean Yaghmour
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Patent number: 11157400Abstract: A garbage collection operation can be performed on one or more data blocks of a memory sub-system, where data is stored at the one or more data blocks using a first write mode. In response to determining that the garbage collection operation satisfies a performance condition, a determination is made as to whether a data block of a cache area of the memory sub-system satisfies an endurance condition, where data is stored at the data block of the cache area using a second write mode. A write mode for the data block of the cache area is changed from the second write mode to the first write mode responsive to determining that the data block satisfies the endurance condition. The data block of the cache area is then used in the garbage collection operation.Type: GrantFiled: January 8, 2020Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe