Abstract: A data storage device is provided. The data storage device includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping tables. The memory controller receives a host command from a host, wherein the host command includes one or more pieces of data and one or more corresponding logical addresses. The memory controller writes the data of the host command into active blocks of the flash memory. In response to the memory controller changing the active blocks into unsaved data blocks and a number of the unsaved data blocks being greater than or equal to an unsaved data block count threshold, the memory controller segmentally updates mapping relationships of the data in the unsaved data blocks, and writes the updated group-mapping tables into the flash memory.

Abstract: A processor includes a cryptographic engine to control access, using an secure region key identifier (ID), to one or more memory range of memory allocable for flexible conversion to secure pages of architecturally-protected memory regions, and a processor core. The processor core is to, responsive to receipt of a request to access the memory, perform a walk of page tables and extended page tables to translate a linear address of the request to a physical address of the memory. The processor core is further to determine that the physical address corresponds to an secure page within the one or more memory range of the memory, that a first key ID located within the physical address does not match the secure region key ID, and issue a page fault and deny access to the secure page in the memory.

Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

Abstract: Method and apparatus for enhancing power cycle performance of a storage device, such as a solid-state drive (SSD). In some embodiments, map data that describe the contents of a non-volatile memory (NVM) are arranged as snapshots and intervening journal updates. During a scram interval in which the storage device transitions to a powered down condition, the snapshots and journal updates for primary segments with high client interest are updated prior to storage to the NVM. During a reinitialization interval in which the storage device transitions to a powered up condition, the updated primary segments are loaded, after which the storage device provides the client device with an operationally ready notification. Remaining secondary segments are updated and loaded after the notification. The primary segments are identified based on a detected workload from the client device. Configuration changes can further be made based on the detected workload.

Abstract: An apparatus in an illustrative embodiment comprises a host device configured to communicate over a network with at least first and second storage systems each comprising a plurality of storage devices. The first and second storage systems are configured to participate in a replication process in which one or more logical storage volumes are replicated from the first storage system to the second storage system. The host device is further configured to execute at least one application, and for each of a plurality of input-output operations generated by the application, to determine a replication status of a particular portion of a given one of the logical storage volumes to which the input-output operation is directed, and to control cloning of the input-output operation based at least in part on the replication status of the particular portion of the given logical storage volume.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

Abstract: A method, computer program product, and computer system for creating, by a computing device, a logical unit number (LUN) on a storage array node of a storage system. An identifier of the LUN of the storage array node may be provided to a computing system, wherein the computing system includes one of a host, a server, and the storage array node. An access control list (ACL) of the computing system may be created. The ACL of the computing system may be applied to the LUN based upon, at least in part, the identifier. The LUN may be discovered and mapped at the computing system. It may be determined that the computing system has failed. The ACL of the computing system that has failed may be removed from the LUN to prevent the computing system that has failed from accessing the LUN.

Abstract: Reclaiming storage space in a tape emulation unit includes determining portions of a tape image of the tape emulation unit that correspond to data/files that have expired, for each of the portions that have expired, overwriting each of the portions with a same value, and the tape emulation unit performing at least one of: compression or deduplication on each of the portions to reclaim storage space maintained by each of the portions. The same value may be zeros. Expiration information may be provided by header information on the tape image. The expiration information may be written by a host computer coupled to the tape emulation unit. The host computer may determine portions that have expired based on the header information. The host computer may run tape management software. The tape emulation unit may determine portions that have expired based on the header information.

Abstract: In a non-volatile memory (NVM) persistence method, a memory controller maintains a plurality of memory write instruction sets that are locked separately for persistence of write operations. A credit value for monitoring a quantity of completed write instructions is configured for each of the plurality of memory write instruction sets, and a credit value is also configured for each of a plurality of medium write instruction sets maintained by a medium controller and corresponding respectively to the memory write instruction sets. After a memory write instruction set is locked in response to a persistence query, the credit value of a corresponding medium write instruction set is used as means for the memory controller to determine whether the write instructions in the locked memory write instruction set have been completed by the medium controller.

Abstract: Methods and systems for an enhanced restripe mechanism are provided. A system for an enhanced restriping mechanism includes a data storage module that stripes data across a plurality of storage devices, wherein the plurality of storage devices are arranged into a plurality of storage pools and the data is distributed across the plurality of storage pools. Also, the system may include a movement detection module that detects changes in the arrangement of the plurality of storage devices that would cause the data on a storage device in the plurality of storage devices to be moved onto other storage devices in the plurality of storage devices. Further, the system may include a restriping module that restripes disk data from the storage device in the plurality of storage devices onto the other storage devices in response to the detected change based on access characteristics of the data.

Abstract: The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions to determine a frequency rate for tracking changed data of a virtual machine (VM), track the changed data at the determined frequency rate, receive a request to generate a recovery point associated with a specified time, and, responsive to receiving the request to generate the recovery point associated with the specified time, generate the recovery point.

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

Abstract: A digital sensor stream is received from a sensor. A domain transform is performed on the digital sensor stream to produce first and second substreams. The first substream is larger than the second substream. The first substream is stored in cold storage and the second substream is stored in a second storage that has faster access times than the cold storage. Deep machine learning is performed on the second substream, the results of which may be stored in the second storage.

Abstract: Methods, apparatus, and processor-readable storage media for classification of storage systems and users thereof using machine learning techniques are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; classifying one or more of the storage systems by applying a first set of machine learning techniques to the processed input data; classifying one or more respective users of the classified storage systems by applying a second set of machine learning techniques to the processed input data associated with the classified storage systems; and outputting, via one or more user interfaces, at least a portion of the storage system classifications and at least a portion of the user classifications to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.