Patents Examined by Hau H. Nguyen
  • Patent number: 10395337
    Abstract: A by-divided area reduction ratio calculation unit determines a reduction ratio based on a deformation parameter for image deformation processing for each of a plurality of divided areas constituting an input image. A by-divided area reduction unit reduces, based on the reduction ratio determined for each of the divided areas, an image in the divided area, and stores the reduced image in a storage unit. A deformation unit performs image deformation processing based on the deformation parameter for the reduced image in the divided area stored in the storage unit.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 27, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Akihiro Takamura
  • Patent number: 10387993
    Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Prashant D. Chaudhari, Michael N. Derr, Arthur J. Runyan
  • Patent number: 10387992
    Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 20, 2019
    Assignee: Intel corporation
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Pattabhiraman K, Matthew B. Callaway
  • Patent number: 10372400
    Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 6, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Theodore F. Emerson, David F. Heinrich, Kenneth T. Chin
  • Patent number: 10373283
    Abstract: An information handling system includes a host processing system and a management controller. The host processing system includes a main processor that instantiates a management controller agent, a graphics processing unit (GPU), and a GPU throttle module. The management controller accesses the management controller via a first interface to obtain a performance status from the GPU, determine that the performance status is outside of a status threshold, and direct, via a second interface of the information handling system, the GPU throttle module to throttle the GPU to bring the performance status to within the status threshold.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 6, 2019
    Assignee: Dell Products, LP
    Inventors: Dinesh Kunnathur Ragupathi, John R. Palmer
  • Patent number: 10354623
    Abstract: A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Dileep Marchya, Balamukund Sripada, Srinivas Pullakavi
  • Patent number: 10346945
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 9, 2019
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Patent number: 10346948
    Abstract: A technique for graphics processing, which completes graphics processing of an image loaded from a system memory by performing a series of slice processing steps. A device for graphics processing has an internal vector dynamic memory for buffering slices of pixel data loaded from the system memory. The internal vector dynamic memory has a first buffer for buffering non-overlapped pixel data, which is not reused in a next slice processing step and a second buffer for buffering overlapped pixel data, which is reused in the next slice processing step.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 9, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Weiman Kong, Yuanyuan Wang, Yuwei Gu
  • Patent number: 10346166
    Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Feng Chen, Narayan Srinivasa, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Joydeep Ray, Nicolas C. Galoppo Von Borries, Prasoonkumar Surti, Ben J. Ashbaugh, Sanjeev Jahagirdar, Vasanth Ranganathan
  • Patent number: 10341689
    Abstract: A weighed run-length encoding and decoding method and related devices and encoded bitstream. The encoded bitstream can comprise one or more of the following: a skip command packed into a nybble, the skip command indicating how many transparent pixels which are inserted into the bitstream, wherein there is up to a maximum number of transparent pixels; a solid command packed into a nybble, the solid command indicating how many solid pixels should be inserted into the decoded bitstream, wherein there are up to the maximum number of solid pixels; and a quote command packed into a nybble, the quote command indicating how many quoted pixels should be inserted into the decoded bitstream, wherein there are up to the maximum number of quoted pixels.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 2, 2019
    Inventor: J. Peter Hoddie
  • Patent number: 10338873
    Abstract: Examples disclosed herein relate to a computing device. In one aspect, the computing device may include a housing including a first point and a second point spatially separated from each other, a first and second wireless communications modules, and a controller. A first waveguide may couple the first point to an input of the first wireless communications module, where an output of the first wireless communications module may be coupled to an input of the controller. A second waveguide may couple the second point to an output of the second communications module, where an input of the second communications module may be coupled to an output of the controller.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 2, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Isaac Lagnado
  • Patent number: 10332231
    Abstract: A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangoak Woo, Jongpil Son, Seungcheol Baek, Soojung Ryu
  • Patent number: 10324844
    Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 18, 2019
    Assignee: Apple Inc.
    Inventors: Anthony P. DeLaurier, Owen C. Anderson, Michael J. Swift, Aaftab A. Munshi, Terence M. Potter
  • Patent number: 10318232
    Abstract: Computer-implemented systems, methods, and computer-readable media are provided for providing virtual monitors. In accordance with some embodiments, a number of virtual monitors in which to provide a virtual desktop and a characteristic of one of the virtual monitors can be identified. A virtual monitor can then be generated based on the characteristic, and a portion of the virtual desktop can be assigned to the virtual monitor based at least in part on the identified number. An image of the portion of the virtual desktop can then be captured from the virtual monitor, and provided for presentation on a monitor of a client device.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 11, 2019
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Rakesh Kumar, Chandrasekhara Reddy
  • Patent number: 10311626
    Abstract: A GPU filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the GPU determines if the graphics workload would require the GPU shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. The GPU can further determine if the shaders are processing more than one graphics workload at the same time, such that the performance characteristics of each individual graphics workload cannot be effectively isolated. The GPU then profiles and stores resource allocations for a plurality of shaders for processing the filtered graphics workloads, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rashad Oreifej, Angel E. Socarras, Mark Russell Anderson, Randy Wayne Ramsey
  • Patent number: 10310768
    Abstract: An apparatus includes a memory and a circuit. The memory may be configured to store data. The circuit generally has a buffer and may be configured to (i) fetch a kernel from the memory, where the kernel may have a plurality of kernel values, (ii) fetch a block from the memory to the buffer, where the block may have a plurality of input tiles and each of the input tiles may have a plurality of input values in multiple dimensions, (iii) calculate a plurality of intermediate values in parallel by multiplying the input tiles read from the buffer with a corresponding one of the kernel values and (iv) calculate an output tile that may have a plurality of output values based on the intermediate values.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 4, 2019
    Assignee: Ambarella, Inc.
    Inventors: Sameer M. Gauria, Peter Verplaetse
  • Patent number: 10304420
    Abstract: An electronic apparatus, an image compression method thereof, and a non-transitory computer readable medium are provided. The electronic apparatus includes an image inputter configured to receive image data, a memory configured to store data, and a processor configured to convert a pixel value of a frame constituting the image data received by the image inputter to a first data value using a preset algorithm, to determine offset for reducing the number of bits of the first data value based on a range of the converted first data value, to add the determined offset to the first data value to generate a second data value, and to store compressed data formed by compressing the generated second data value in the memory, wherein a header of the compressed data includes information on the number of bits of the second data value and the determined offset.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: In-hwan Kim
  • Patent number: 10304156
    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 28, 2019
    Assignee: Google LLC
    Inventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
  • Patent number: 10296400
    Abstract: The application programming interface permits an application to specify resources to be used by shaders, executed by the GPU, through a data structure called the “root arguments.” A root signature is a data structure in an application that defines the layout of the root arguments used by an application. The root arguments are a data structure resulting from the application populating locations in memory according to the root signature. The root arguments can include one or more constant values or other state information, and/or one or more pointers to memory locations which can contain descriptors, and/or one or more descriptor tables. Thus, the root arguments can support multiple levels of indirection through which a GPU can identify resources that are available for shaders to access.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 21, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amar Patel, Matthew D. Sandy, Yuri Dotsenko, Jesse T. Natalie, Max A. McMullen
  • Patent number: 10282811
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Balaji Vembu