Patents Examined by Hau H. Nguyen
  • Patent number: 10310768
    Abstract: An apparatus includes a memory and a circuit. The memory may be configured to store data. The circuit generally has a buffer and may be configured to (i) fetch a kernel from the memory, where the kernel may have a plurality of kernel values, (ii) fetch a block from the memory to the buffer, where the block may have a plurality of input tiles and each of the input tiles may have a plurality of input values in multiple dimensions, (iii) calculate a plurality of intermediate values in parallel by multiplying the input tiles read from the buffer with a corresponding one of the kernel values and (iv) calculate an output tile that may have a plurality of output values based on the intermediate values.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 4, 2019
    Assignee: Ambarella, Inc.
    Inventors: Sameer M. Gauria, Peter Verplaetse
  • Patent number: 10311626
    Abstract: A GPU filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the GPU determines if the graphics workload would require the GPU shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. The GPU can further determine if the shaders are processing more than one graphics workload at the same time, such that the performance characteristics of each individual graphics workload cannot be effectively isolated. The GPU then profiles and stores resource allocations for a plurality of shaders for processing the filtered graphics workloads, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the GPU.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rashad Oreifej, Angel E. Socarras, Mark Russell Anderson, Randy Wayne Ramsey
  • Patent number: 10304156
    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 28, 2019
    Assignee: Google LLC
    Inventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
  • Patent number: 10304420
    Abstract: An electronic apparatus, an image compression method thereof, and a non-transitory computer readable medium are provided. The electronic apparatus includes an image inputter configured to receive image data, a memory configured to store data, and a processor configured to convert a pixel value of a frame constituting the image data received by the image inputter to a first data value using a preset algorithm, to determine offset for reducing the number of bits of the first data value based on a range of the converted first data value, to add the determined offset to the first data value to generate a second data value, and to store compressed data formed by compressing the generated second data value in the memory, wherein a header of the compressed data includes information on the number of bits of the second data value and the determined offset.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: In-hwan Kim
  • Patent number: 10296400
    Abstract: The application programming interface permits an application to specify resources to be used by shaders, executed by the GPU, through a data structure called the “root arguments.” A root signature is a data structure in an application that defines the layout of the root arguments used by an application. The root arguments are a data structure resulting from the application populating locations in memory according to the root signature. The root arguments can include one or more constant values or other state information, and/or one or more pointers to memory locations which can contain descriptors, and/or one or more descriptor tables. Thus, the root arguments can support multiple levels of indirection through which a GPU can identify resources that are available for shaders to access.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 21, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amar Patel, Matthew D. Sandy, Yuri Dotsenko, Jesse T. Natalie, Max A. McMullen
  • Patent number: 10282811
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Balaji Vembu
  • Patent number: 10275848
    Abstract: The sequence of instructions for a shader program 60 to be executed by a shader core of a graphics processor is divided into an initial set of instructions 61 that perform “global” common expressions of the shader program, a set of instructions 62 in the shader program that perform expressions that are common to a given work group within a set of work items that the shader program is to process, and a main instruction sequence 63 that needs to be executed independently for each work item. Execution threads are then able to start executing the shader program either at the beginning of the global common expressions 64, or at the beginning of the work group common expressions 65, or at the beginning of the main instruction sequence 66.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 30, 2019
    Assignee: Arm Limited
    Inventor: Peter William Harris
  • Patent number: 10269325
    Abstract: A display system for connecting a computer to a display having EDID information. The display system includes a graphics card and an adapter. The graphics card is in communication with the computer and includes: a graphics processor; a graphics card controller coupled to the graphics processor; and a memory coupled to the graphics card controller and the graphics processor. The adapter has an adapter controller, the adapter coupled to the display and coupled to the graphics card, wherein the graphics card controller is configured to query the EDID information from the display and store the EDID information as emulated EDID information in the memory and further wherein the graphics processor reads the emulated EDID information from the memory rather than from the display.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 23, 2019
    Assignee: ADVOLI LIMITED
    Inventors: Clas Gerhard Sivertsen, Paal Fure Torkehagen
  • Patent number: 10262386
    Abstract: A method of rendering an image is disclosed. A plurality of non-overlapping regions of the image is received, each region being associated with a fill compositing stack comprising a plurality of levels to be composited to determine color data of said region, each level being defined by a compositing operation and a color operand. Equivalent ones of the compositing stacks are identified, the equivalent compositing stacks being defined by equivalent sets of graphical commands applied to different color operands. Regions associated with the equivalent compositing stacks are selected. Pixels corresponding to the selected regions are combined into a data structure. The pixels are concurrently rendered using the data structure to render the image.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 16, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Lena Qunying Ye Qian
  • Patent number: 10255876
    Abstract: A method and information handling system including a display device connector for connecting to a digital display device, a controller executing instructions of an impedance mismatch control system for determining impedance differences along an operative connection from the display device connector to the digital display device, where the controller receives a display device connector impedance measurement and a second impedance measurement from a point further along the operative connection between the display device connector and the digital display device, and the controller executes the impedance mismatch control system to determine an impedance mismatch exists from the impedance difference between the display device connector and the point further along the operative connection between the display device connector and the digital display device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Dell Products, LP
    Inventors: Ching-Wei Chang, I-Yu Chen
  • Patent number: 10242311
    Abstract: A convolution engine, such as a convolution neural network, operates efficiently with respect to sparse kernels by implementing zero skipping. An input tile is loaded and accumulated sums are calculated for the input tile for non-zero coefficients by shifting the tile according to a row and column index of the coefficient in the kernel. Each coefficient is applied individually to tile and the result written to an accumulation buffer before moving to the next non-zero coefficient. A 3D or 4D convolution may be implemented in this manner with separate regions of the accumulation buffer storing accumulated sums for different indexes along one dimension. Images are completely processed and results for each image are stored in the accumulation buffer before moving to the next image.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 26, 2019
    Assignee: VIVANTE CORPORATION
    Inventor: Mankit Lo
  • Patent number: 10235740
    Abstract: An information handling system communicates visual information to a display in a first pixel value format and the display converts the first pixel formation to a native format with a graphics processing unit. The graphics processing unit adapts its programming to convert various input pixel values into desired native formats, such as by converting High Definition input into Ultra High Definition native format. The information handling system and display coordinate through configuration information to identify and program the display graphics processor to perform desired pixel conversion.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 19, 2019
    Assignee: Dell Products L.P.
    Inventor: Srinivas Kamepalli
  • Patent number: 10223961
    Abstract: A method for displaying images on an active matrix screen, i representing a pointer of a current row and each pixel comprising a memory and a display component comprises controlling the brightness of the pixels by a binary word comprising a number of bits written successively into the memory and by controlling the display component as a function of a state of the bit written into the memory, the bits of each binary word being ranked by their weight from j=1 to j=P. The writes are sequenced: from a current row i, writing on the rows i+2j, from j=1 to j=P, the bit of weight j of each binary word associated with different pixels of rows i+2j; repeating, 2P?1 times, the writes mentioned above by shifting the pointer i of the current row by one unit on each repetition; i being determined modulo 2P?1 to lie between 1 and 2P?1.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: March 5, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Josep Segura Puchades
  • Patent number: 10217184
    Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 26, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: John Erik Lindholm, Brett W. Coon, Stuart F. Oberman, Ming Y. Siu, Matthew P. Gerlach
  • Patent number: 10204396
    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 12, 2019
    Assignee: Google LLC
    Inventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
  • Patent number: 10204051
    Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Zeev Offen, Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Altug Koker, Opher Kahn
  • Patent number: 10204392
    Abstract: Techniques for graphics processing unit (GPU) partitioning for virtualization are described herein. In one or more implementations, a GPU partitioning manager of a host device obtains a request for a virtual machine having GPU functionality. In particular, the request specifies the GPU functionality in terms of different GPU capabilities. These different capabilities correspond to segments of a GPU model that represents GPU functionality and is used to govern interactions between virtual machines and GPUs. The GPU partitioning manager determines whether GPUs of the host device are available to satisfy the request based on the specified capabilities. If so, the GPU partitioning manager allocates a portion of the determined available GPUs to the virtual machine to configure the virtual machine with a GPU partition having the functionality. The virtual machine configured with the GPU partition can then be exposed to provide GPU-processed data to a GPU partition requestor.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 12, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hadden Mark Hoppert, Christopher L. Huybregts, Jacob Kappeler Oshins
  • Patent number: 10176783
    Abstract: A computer-driven wearable display device incorporating a display engine for presenting virtual images to wearers is interconnected with a computer-driven portable display device incorporating a display screen for presenting real images to the wearers of the wearable display device. An applications management and communication system including an external manager application residing on the portable display device provides for managing and launching applications residing on the wearable display device through the user interface of the portable display device.
    Type: Grant
    Filed: January 4, 2014
    Date of Patent: January 8, 2019
    Assignee: Vuzix Corporation
    Inventors: Paul J. Travers, Michael McCrackan
  • Patent number: 10176739
    Abstract: An aspect of the present invention proposes a method for performing partial refresh on display panels. According to one or more embodiments of the present invention, the display panels may be implemented as self-refreshing display panels communicatively coupled with a computing device that generates graphical data for display in the display panel. To perform partial refresh, consecutive frames are compared to identify the portions of the frames with updated material. In one or more embodiments, only the pixels corresponding to the updated portion(s) are refreshed in the display panel.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 8, 2019
    Assignee: Nvidia Corporation
    Inventors: Gaurav Singh, Radhika Ranjan Soni
  • Patent number: 10163179
    Abstract: An apparatus and method are described for cloud-based graphics updates. For example, one embodiment of an apparatus comprises a system optimization agent to detect a graphics application installed on the apparatus, the system optimization agent to responsively transmit, over a network, information related to the graphics application including a new graphics application or a new version of an existing graphics application. The apparatus may further comprise the system optimization agent to receive, over the network, optimized program code comprising one or more optimizations to specified portions of a graphics driver, where the one or more optimizations relate to the graphics application.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Travis T. Schluesser, Robert B. Taylor, Abhishek Venkatesh, Daniel H. Walsh