Patents Examined by Hau H. Nguyen
  • Patent number: 9984491
    Abstract: Provided is a method of managing commands, which includes receiving a frame buffer object (FBO) change command, comparing an FBO designated by the FBO change command with a FBO currently processed by a graphics processing unit (GPU) to determine whether the two FBOs are the same as each other, and managing the FBO change command or a flush command based on a result of the comparison.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangoak Woo, Jeongae Park, Minkyu Jeong, Minyoung Son, Seokyoon Jung, Jeongwook Kim, Soojung Ryu
  • Patent number: 9965318
    Abstract: The disclosure generally relates to principal component analysis (PCA) computation and, more particularly, to concurrent PCA computation. In one embodiment, a plurality of concurrent PCA requests are received by a server. An input matrix for each of the concurrent PCA requests is computed using a general purpose-graphical processing unit (GP-GPU) by the server. Further, tridiagnolization on the input matrix is performed on each of the concurrent PCA requests by a general purpose-graphical processing unit (GP-GPU) in the server to generate a tridiagonal matrix for each of the concurrent PCA requests. Furthermore, a plurality of eigen values and corresponding eigen vectors are computed for the tridiagonal matrix of each of the concurrent PCA requests by the server and subsequently back transformation of the eigen values and the eigen vectors is performed by the server for each of the concurrent PCA requests to obtain associated principal components.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: May 8, 2018
    Assignee: Tata Consultancy Services Limited
    Inventors: Easwara Naga Subramanian, Amit Kalele, Anubhav Jain
  • Patent number: 9928639
    Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 27, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Michael Toksvig, Erik Lindholm
  • Patent number: 8009175
    Abstract: Improved methods are provided for calibrating color on a color display coupled to a computer, which are useful for obtaining calibrated data in a virtual proof network for enabling different color devices to render consistent color. Methods involve user interactions with screens on the display to set color display parameters. An apparatus is also provided for calibrating a sensor which may be used for measuring color of a display in one or more of these methods.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: August 30, 2011
    Assignee: Rah Color Technologies LLC
    Inventor: Richard A. Holub
  • Patent number: 7999815
    Abstract: One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: August 16, 2011
    Assignee: NVDIA Corporation
    Inventors: Duncan A. Riach, Leslie E. Neft, Michael A. Ogrinc, Tyvis C. Cheung
  • Patent number: 7999820
    Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 16, 2011
    Assignee: NVIDIA Corporation
    Inventors: Adam Clark Weitkemper, Steven E. Molnar, Mark J. French, Cass W. Everitt
  • Patent number: 7999814
    Abstract: An arithmetic processing unit in a graphics processor alternately executes a process of a first image processing which generates a main image of an application, i.e., a base image and a process of a second image processing which generates a display image eventually displayed by performing a desired processing of the base image. Processing time for the process of the first image processing is designated by a first process executing unit in a main processor which requests execution of the process of the first image processing. Processing time for the process of the second image processing is predetermined. The first process executing unit further determines an address of storage area in a frame buffer storing the base image and, upon determination, transmits to the second process executing unit which requests execution of the process of the second image processing.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: August 16, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Sachiyo Aoki
  • Patent number: 7995067
    Abstract: A storage buffer attached to an image processor for stereo image processing. The processor compares a first image and a second image. The storage buffer stores image data of the second image. The storage buffer includes: a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer. The data-shifting hardware mechanism includes preferably digital multiplexers with respective selectable inputs from adjacent and non-adjacent columns of data within the storage buffer and selectable inputs from adjacent rows of data within the storage buffer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 9, 2011
    Assignee: Mobileye Technologies Limited
    Inventor: Mois Navon
  • Patent number: 7995068
    Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: August 9, 2011
    Inventors: Thomas E. Willis, Steven L. Midford
  • Patent number: 7995069
    Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: August 9, 2011
    Assignee: Nintendo Co., Ltd.
    Inventors: Timothy Van Hook, Farhad Fouladi
  • Patent number: 7990389
    Abstract: A graphic system includes a pipelined graphic engine for generating image frames for display. The pipelined graphic engine includes a geometric processing stage for performing motion extraction, and a rendering stage for generating full image frames at a first frame rate for display at a second frame rate. The second frame rate is higher than the first frame rate. A motion encoder stage receives motion information from the geometric processing stage, and produces an interpolated frame signal representative of interpolated frames. A motion compensation stage receives the interpolated frame signal from the motion encoder stage, and the full image frames from the rendering stage for generating the interpolated frames. A preferred application is in graphic systems that operate in association with smart displays through a wireless connection, such as in mobile phones.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: August 2, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimiliano Barone
  • Patent number: 7990391
    Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 7973806
    Abstract: A reproducing apparatus includes a graphics processing unit that outputs graphics data of an RGB color space, a video decoder that outputs video data of a YUV color space, a conversion unit that converts a color space of the graphics data from the RGB color space to the YUV color space, a blending process unit that executes a blending process in which the graphics data that is converted to the YUV color space and the video data of the YUV color space are blended on the YUV color space, and a picture data output unit that outputs picture data, which is obtained by the blending process, to a display apparatus.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Kuno
  • Patent number: 7956864
    Abstract: An imaging system for use with an external memory system, an external memory system for use with an imaging system, and methods for archiving digital content are provided. The imaging system has a source of content data files and a communications link adapted to exchange data with the external memory system. A processor is adapted to prepare content data files for archival storage on the external memory system and to cause the external memory system to store the prepared content data files.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: June 7, 2011
    Assignee: Eastman Kodak Company
    Inventors: John R. Fredlund, Joseph A. Manico
  • Patent number: 7952588
    Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 31, 2011
    Assignee: Qualcomm Incorporated
    Inventors: Guofang Jiao, Brian Evan Ruttenberg, Chun Yu, Yun Du
  • Patent number: 7944452
    Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 17, 2011
    Assignee: NVIDIA Corporation
    Inventors: Adam Clark Wietkemper, Steven E. Molnar, Mark J. French, Cass W. Everitt
  • Patent number: 7932913
    Abstract: An object collation method comprising a registration procedure for registering the registered data of a registered object in a database, and a collation procedure for collating the input image of a target object with the registered data. The registration procedure includes a step of storing the three-dimensional shape of the registered object and a texture space defined by a texture group indicating the luminance and/or color information of each position of the object surface under various illumination conditions. The collation procedure includes the steps of: generating an illumination fluctuation space defined by the image group under the various illumination conditions, at the location and position of the target object in the input image from the three-dimensional shape and the texture space; and collating the target object and the registered object based on the distance between the illumination fluctuation space and the input image.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: April 26, 2011
    Assignee: NEC Corporation
    Inventor: Rui Ishiyama
  • Patent number: 7924296
    Abstract: A system for processing image data from a plurality of images is disclosed. The invention involves alpha blending of two images of different resolution and color space utilizing shared logic for multiple image streams and without display storage frame buffer. The invention utilizes Direct Memory Access (DMA) fetching module for fetching image data from source images or from source image memory areas and transferring the data to another memory area without having to go through a central processing unit or display storage frame buffer. The DMAs are configured with direct registers or memory mapped descriptors as to the location of the source data. The DMA channels of the DMA module will fetch a portion of the source images (tiling) utilizing a link list or series of descriptors in a certain fetching order. The DMA modules can perform the alpha blending on the fetched image data.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: April 12, 2011
    Assignee: Mtekvision Co., Ltd.
    Inventor: Rabindra Guha
  • Patent number: 7920141
    Abstract: The present invention relates to a rasterizer interpolator. In one embodiment, a setup unit is used to distribute graphics primitive instructions to multiple parallel rasterizers. To increase efficiency, the setup unit calculates the polygon data and checks it against one or more tiles prior to distribution. An output screen is divided into a number of regions, with a number of assignment configurations possible for various number of rasterizer pipelines. For instance, the screen is sub-divided into four regions and one of four rasterizers is granted ownership of one quarter of the screen. To reduce time spent on processing empty times, a problem in prior art implementations, the present invention reduces empty tiles by the process of coarse grain tiling. This process occurs by a series of iterations performed in parallel. Each region undergoes an iterative calculation/tiling process where coverage of the primitive is deduced at a successively more detailed level.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: April 5, 2011
    Assignee: ATI Technologies ULC
    Inventor: Mark M. Leather
  • Patent number: 7916151
    Abstract: Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: March 29, 2011
    Assignee: NVIDIA Corporation
    Inventors: Emmett M. Kilgariff, Rui M. Bastos