Abstract: A method includes detecting, by a coexistence controller of a system on a chip (SoC), an occurrence of a coexistence event of an SoC component; providing, by the coexistence controller, an indication of the occurrence of the coexistence event to a coexistence coordinator; and changing, by the coexistence controller, an operating point of the SoC from a current operating point to a new operating point responsive to receiving an operating point change request from the coexistence coordinator.

Abstract: An exemplary system includes a processor, a wearable device comprising a plurality of slots, and a first module including a plurality of detectors and a module control circuit. The processor is configured to successively transmit, to each slot of the plurality of slots, a command to enable a respective module located in each slot. The processor is further configured to determine, based on an acknowledgment received from the module control circuit, that the first module is enabled and located in a first slot, and to successively transmit, based on the determining that the first module is enabled and located in the first slot, a plurality of detector address identifiers. The module control circuit is configured to successively place the plurality of detectors into an enumeration mode in which each detector of the plurality of detectors is assigned a different detector address identifier of the plurality of detector address identifiers.

Abstract: Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

Abstract: A network interface controller (NIC) capable of efficient operation management for host accelerators is provided. The NIC can be equipped with a host interface and triggering logic block. During operation, the host interface can couple the NIC to a host device. The triggering logic block can obtain, via the host interface from the host device, an operation associated with an accelerator of the host device. The triggering logic block can determine whether a triggering condition has been satisfied for the operation based on an indicator received from the accelerator. If the triggering condition has been satisfied, the triggering logic block can obtain a piece of data generated from the accelerator from a memory location and execute the operation using the piece of data.

Abstract: A system and method checks packetized data retrieved from a bus that is ordinarily considered reliable that was already error checked and/or corrected before being placed on the bus by applying a hash or checksum or other function to each packet to produce a packet checksum and then applying another function to the ordered packet checksums and comparing the result to one sent by the device that checked and/or corrected, and sent, the data packets.

Abstract: A system for increasing the speed and reducing the time to obtain a required amount of data, from a secondary storage device, for a digital computer, BASED UPON measures to improve the time efficiency of I/O request processing by improving the timing and sequence of transfers, thus improving the efficiency of mass storage devices.

Abstract: An interconnected computer system includes a Peripheral Component Interconnect Express (PCIe) fabric, a first computer system communicatively coupled to the PCIe fabric, a second computer system communicatively coupled to the PCIe fabric, and a shared single-access hardware resource coupled to the PCIe fabric. The first computer system includes a first processor and first memory coupled to the first processor configured to store a first flag indicating a desire of the first computer system to access the shared single-access hardware resource and a turn variable indicating which of the first computer system and the second computer system has access to the shared single-access hardware resource. The second computer system includes a second processor and second memory coupled to the second processor configured to store a second flag indicating a desire of the second computer system to access the shared single-access hardware resource.

Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.

Abstract: An input/output station is provided. The input/output station is for a fieldbus system with a fieldbus coupler, which has a system bus interface and a fieldbus interface. The input/output station comprising a plurality of slots for pluggable input/output devices. One or more placeholder devices are also pluggable into the plurality of slots besides the input/output devices. An empty slot is also admissible for the plurality of slots. The fieldbus coupler comprises firmware which is configured for a full configuration of the input/output station. The firmware is configured to communicate with a control station in such a way that the fieldbus coupler receives the full configuration of the input/output station as a planned target configuration from the control station. The firmware is configured to confirm a full configuration of the input/output station in an operating mode irrespective of the actual occupancy of the input/output station.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.

Abstract: A Controller Area Network (CAN) system, method, and circuit are provided with a dual mode bus line termination circuit connected between signal lines of a serial bus and optimized for both differential and single-ended communication modes over the serial bus, where the dual mode bus line termination circuit includes first and second resistance termination paths connected in parallel between first and second bus wires of the serial bus to provide an odd mode termination impedance (RODD) that matches an impedance of the serial bus when operating in the differential communication mode, and to also provide an even mode termination impedance (REVEN) that matches an impedance of the serial bus when operating in the single-ended communication mode.

Abstract: A device for a serial bus system. The device includes a reception block for receiving a signal from a bus of the bus system. The signal is based on a transmission signal via which a message is exchanged between user stations. The reception block receives, in a first communication phase, the signal using a first reception threshold, and in a second communication phase, receives the signal using a second reception threshold. The device includes an evaluation block for evaluating the signal from the bus using a switchover reception threshold that differs from the first and second reception thresholds, and a reception threshold switching block for the time-limited switchover of the reception threshold of the reception block from the first reception threshold to the second reception threshold when the evaluation block detects the bus level for data of the transmission signal, using the switchover reception threshold in the signal.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: A microcontroller system comprising a master microcontroller unit, a further module and a general purpose input/output. In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.

Abstract: Disclosed are a USB data communication method and device based on a hybrid USB Network. The USB data communication method based on a hybrid USB Network includes following steps executed by the docking station terminal: obtaining a USB data monitoring command carrying an operation mode; when the operation mode is an automatic mode, monitoring a data communication status of a USB input and output interface; when the data communication status is a no input and output information status, monitoring a data of a network input data interface of a network module in the docking station terminal; when the network input data interface obtains a data sending request sent by a client terminal via the hybrid USB Network, in which the data sending request includes network data and a target transmission device, converting the network data into a USB communication data via a soft switching module in the docking station terminal.

Abstract: A failure recommendation system for a command line interface (CLI) uses machine learning to predict the most likely command to correct an unsuccessful or failed attempt to perform an intended operation using the CLI. The failure recommendation system is based on a conditional probability model trained on failure-success pairs of commands from CLI telemetry data to learn the most likely command to remediate a failure. The conditional probability model predicts the most likely command based on a failure type and the failed command. The failure type is identified through a failure type classifier and is used to select the most likely command to remediate a failure from the different events that may lead to a failure.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.

Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.