Abstract: Disclosed is an industrial control device including a point-to-point backplane/point module architecture providing RIUP (Removal and Insertion Under Power) functionality where data communications between modules is maintained after the removal of a point module from the backplane. According to an exemplary embodiment, a backplane includes a plurality of passive mechanical bypass switches controlled by the insertion and removal of respective point modules, whereby data communicated bypass a removed point module interface and point-to-point data communications are provided to an inserted point module after an initial routine is executed by a microcontroller associated with the inserted point module.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: A cable includes a first plug, a second plug, and a controller. The first plug is configured to be connected with a host. The second plug is configured to be connected with a device. The controller is coupled between the first plug and the second plug, and is configured to monitor a connection message transferred between the host and the device, and to determine, according to the connection message, a transfer mode that the host and the device is to enter, and to set a plurality of electrical parameters to be a corresponding one set in a plurality of sets of predetermined parameters.

Abstract: A computer-implemented method, according to one embodiment, includes: causing a first subset of pulse width modulators in a crossbar array of memory cells to apply respective pulses to the crossbar array together at a same start time and end the respective pulses according to a predetermined distribution of times correlated to stored pulse width data for each pulse width modulator. The method also includes causing a second subset of pulse width modulators in the crossbar array to apply pulses to the crossbar array according to the predetermined distribution of times correlated to stored pulse width data for each pulse width modulator and end the respective pulses together at a same end time.

Abstract: A twisted-pair cable serial console communication adapter system includes a networking device including a first serial console connector, a twisted-pair cable including a first twisted-pair cable connector, and a first twisted-pair cable serial console communication adapter device that is connected to the first serial console connector and the first twisted-pair cable connector. The first twisted-pair cable serial console communication adapter device receives first signals via a first transmit pin on the first serial console connector, and provides the first signals to a first twisted-pair conductor in the twisted-pair cable. The first twisted-pair cable serial console communication adapter device also receives second signals via a second twisted-pair conductor in the twisted-pair cable, and provides the second signals to a first receive pin on the first serial console connector.

Abstract: Circuits, methods, and apparatus that can allow chipsets in an electronic device to share information such that they can more efficiently utilize resources that are available in the electronic device. One example can provide a bus that is shared by three or more chipsets in an electronic device. This shared bus can be used by the chipsets in the electronic device to communicate and negotiate for the utilization of resources of the electronic device.

Abstract: A connector includes a first pin which is configured to indicate an in-service signal, a second pin which is configured to indicate a power supply signal, a third pin which is configured to indicate a clock signal, and a fourth pin; the first pin which is configured to indicate a PCIe port signal; the first pin, the second pin, the third pin, and the fourth pin have an equal length; and the connector includes a first face and a second face, a limiting structure is arranged on the first face, the limiting structure is a boss or a groove, and the first pin is located in the middle of the first face.

Abstract: The disclosure provides a USB device, a USB cable, and a USB repeater. The USB cable or the USB device includes a USB connector and the USB repeater. The USB repeater may gain a signal of a differential pin pair of the USB connector. The USB repeater may monitor a signal of a configuration channel pin of the USB connector. The USB repeater selectively runs in one of a plurality of working modes corresponding to a plurality of protocols according to a monitoring result.

Abstract: Disclosed herein are self-aware, self-modifying, autonomous connection mechanisms. Exemplifying intelligent systems introduce some of the embodiments of the autonomous connection mechanism techniques.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: A device and a method for interlinking conventional fieldbus-based automatic control system with IoT at a subordinate position are provided. According to the present disclosure, the interlinking system device comprise a fieldbus connection unit connected to an operation device based on a fieldbus protocol and configured to operate as an input-output device, a fieldbus virtual input-output memory configured to memorize input-output information exchanged with the operation device, an IoT connection unit connected to an IoT platform based on an IoT protocol and configured to operate as an IoT device, a message formation unit configured to apply message metadata received from the IoT platform via the IoT connection unit and a message processing unit configured to process an input-output message based on the message metadata and the input-output information.

Abstract: A method for operating a communications network that includes at least two users that are communicatively connected to one another via a descriptor-based communication system such as Ethernet. For writing data from a writing user into a user to be written, receive descriptors and data are transmitted from the writing user to the user to be written, in the user to be written, the data being written according to the received receive descriptors, and/or for reading data by a reading user from a user to be read, transmit descriptors are transmitted from the reading user to the user to be read, data being read by the user to be read according to the received transmit descriptors and transmitted to the reading user. A communications network and users are also described.

Abstract: An information handling system may include a management controller and information handling resources that are coupled to the management controller via a first communication channel and a second communication channel, each information handling resource having a first communication channel identifier, and each information handling resource having a second communication channel identifier. The management controller may query the information handling resources via the first communication channel to determine a first set of unique identifiers for the information handling resources; query the information handling resources via the second communication channel to determine a second set of unique identifiers for the information handling resources; and based on a comparison between the first set of unique identifiers and the second set of unique identifiers, create a mapping that correlates the first communication channel identifiers with the second communication channel identifiers.

Abstract: The invention relates to a bus-capable device having an input interface and an output interface for connecting to a serial bus, particularly a CAN bus, wherein the input interface and the output interface each have at least one signal line connection, and further having a terminating resistor for terminating the bus and a switch apparatus for switching the terminating resistor active as a function of the connection status of the input and output interfaces, wherein the input interface and the output interface each having a supply voltage connection for providing a supply voltage to the output and/or input interfaces of a respective next bus-capable device and a feedback connection for receiving the supply voltage from an output and/or input interface of a respective next bus-capable device, wherein the switch apparatus has an evaluation circuit for determining the presence of the supply voltage at the feedback connections of the input and output interfaces and an activation circuit for switching the terminati

Abstract: Methods and servers for storing data associated with users and digital items of a recommendation system having access to non-distributed and distributed storages. The server trains a model based for generating first user and item embeddings. The server stores (i) the first user embeddings in the non-distributed storage, and (ii) the first item embeddings in the distributed storage. The server re-trains the model for generating second user and item embeddings. The server stores (i) the second user embeddings in the non-distributed storage in addition to the first user embeddings, and (ii) second item embeddings in the distributed storage instead of the respective first item embeddings by replacing the respective first item embeddings. When the second item embeddings are stored on each node of the distributed storage, the server removes the first user embeddings associated with the first value from the non-distributed storage.

Abstract: A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Abstract: Techniques are described for controlling a sensing state of a device. In an example, a controller of the device receives, at a first time, first input data indicating a first request to disable a sensor of the device. The controller causes the sensor to be disabled and stores first data indicating that the sensor is disabled. The device can also include a processor. The controller sends, to the processor, first output data that causes the processor to read the first data from the controller. At a second time, the controller receives second input data indicating a second request for an operation of the device. The controller stores second data associated with the second request and sends, to the processor, second output data that causes the processor to read the second data from the controller.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

Abstract: A computer-implemented method includes receiving, by a computing device, input activations and determining, by a controller of the computing device, whether each of the input activations has either a zero value or a non-zero value. The method further includes storing, in a memory bank of the computing device, at least one of the input activations. Storing the at least one input activation includes generating an index comprising one or more memory address locations that have input activation values that are non-zero values. The method still further includes providing, by the controller and from the memory bank, at least one input activation onto a data bus that is accessible by one or more units of a computational array. The activations are provided, at least in part, from a memory address location associated with the index.