Abstract: Communication between target devices using protocol commands being carried out by a target device includes accessing a key for mapping of a plurality of defined patterns of stimuli and defined patterns of resultant protocol commands to a plurality of messages. A defined pattern of stimuli is sent from a target device to an initiator device to prompt a resultant defined pattern of protocol commands to be sent from the initiator device to all target devices that identify as the same device. The protocol commands including Small Computer System Interface (SCSI) specification compliant commands. A selected pattern of protocol command stimuli is sent from a first target device to the initiator device to prompt a resultant pattern of protocol commands from the initiator device to all target devices that identify as the same device thereby communicating the mapped message to other target devices.

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

Abstract: An interconnect interface is applied between sockets or between dies. The interconnect interface includes a first transmitter (TX), a first receiver (RX), and an electrical physical layer (EPHY) coupled between the first TX and the first RX. The data provided by a first device is transmitted from the first TX to the EPHY and then received by the first RX to be retrieved by a second device. The first TX includes an arbiter for arbitrating between a plurality of channels of the first device to obtain data from the first device. The first TX includes a packet generator, which packs the data obtained from the first device into a packet to be transmitted through the EPHY. The first TX further includes a first buffer that backs up the data obtained from the first device for retransmission.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: A method, a system, and a server for monitoring status of SSD applied in the server allows a volume management device which has been disabled because of conflict to be used to maintain unchanged information of power indicating control bit when an SSD is unplugged. The unchanged information of power indicating control bit is transmitted to a CPLD and decoder information is obtained from the CPLD. Position of the SSD in the register is set according to the decoder information.

Abstract: Two or more semaphores can be used per queue for synchronization of direct memory access (DMA) transfers between a DMA engine and various computational engines by alternating the semaphores across sequential sets of consecutive DMA transfers in the queue. The DMA engine can increment a first semaphore after performing each DMA transfer of a first set of consecutive DMA transfers and a second semaphore after performing each DMA transfer of a second set of consecutive DMA transfers that is after the first set of consecutive DMA transfers in the queue. Each semaphore can be reset when all the computational engines that are dependent on the respective set of consecutive DMA transfers are done waiting on the given semaphore before performing respective operations. After reset, the first semaphore or the second semaphore can be reused for the next set of consecutive DMA transfers in the queue.

Abstract: Traditionally, servers are interconnected inside a data center using regular network cards. It is desired that high-available network-attached storage arrays have the feature of non-disruptive upgrade (NDU) for software and firmware, while one or more applications are still running IO. With the emergence of SmartNICs, there are many functions available now to SmartNIC that may enhance server and entire solution capabilities. Since SmartNIC is a new emerging technology, there are no adequate solutions currently for NDU while running I/O. The present patent document discloses embodiments for upgrading the SmartNIC software without disruption to the host applications. A shared namespace may be implemented inside an emulated NVMe/PCIe device, such as a data processing unit (DPU) or infrastructure processing unit (IPU), such that multiple instances may be enabled to run both old and new target emulation SPDK-based software together using multiple paths to achieve SmartNIC storage NDU.

Abstract: An electronic device connectable to a network interface device having a plurality of signal lanes may include a first computing device, a second computing device, and an interface to connect the first computing device to a first subset of signal lanes of the plurality of data lanes of the network interface device and connect the second computing device to a second subset of data lanes of the plurality of data lanes of the network computing device.

Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

Abstract: A method and system for realizing a FPGA server, wherein centralized monitoring and managing all SoC FPGA compute nodes within the server by a motherboard, the motherboard comprising: a plurality of self-defined management interfaces for connecting the SoC FPGA compute nodes to supply power and data switch to the SoC FPGA compute nodes; a management network switch module for interconnecting the SoC FPGA compute nodes and supplying management; and a core control unit for managing the SoC FPGA compute nodes through the self-defined management interfaces and a self-defined management interface protocol, and acquiring operating parameters of the SoC FPGA compute nodes to manage and monitor the SoC FPGA compute nodes based on the management interface protocol.

Abstract: The present disclosure discloses a server management framework and a server. The server management framework includes: a management board, wherein the management board comprises a baseboard management controller, a platform controller hub, and a management board complex programming logic device (CPLD), and a first end of the management board CPLD is connected to the platform controller hub; and a motherboard, wherein the motherboard comprises a central processing unit and a motherboard CPLD, a first end of the motherboard CPLD is connected to the central processing unit, and a second end of the motherboard CPLD is connected to a second end of the management board CPLD, so that the baseboard management controller communicates with the management board CPLD through the motherboard CPLD, and the platform controller hub communicates with the baseboard management controller through the motherboard CPLD and the management board CPLD.

Abstract: Memory systems and methods of operating the memory systems are disclose. In one arrangement, a device includes a memory device configured to store first data, a first input/output (I/O) pin, and a serial communication device configured to receive the first data and output the first data. The serial communication device is connected to the first I/O pin via a first device. The device also includes a virtual communication logic configured to receive the first data and output the first data to a communication interface connected to a host device.

Abstract: Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.

Abstract: Disclosed is a signal processing circuit, a contactless connector, a signal processing method and a storage medium.

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device includes a first buffer, a second buffer, and a buffer controller. The first buffer may be configured to store a plurality of first transaction layer packets received from multiple functions. The second buffer may be configured to store a plurality of second transaction layer packets received from the multiple functions. The buffer controller may be configured to, when a first buffer of a switch is full, realign an order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch, based on IDs of the plurality of second transaction layer packets.

Abstract: A communication device mounted in each of a plurality of information processing devices connected to a fabric, the communication device comprises: a serial interface that transmits and receives a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit that acquires the first packet from the serial interface and converts the first packet that has been acquired into a second packet that is transmitted and received via the fabric among a plurality of the information processing devices sharing a memory space that is virtually extended by using a device identifier specific to each of the information processing devices; a fabric communication unit that transmits and receives the second packet via the fabric; and a completer unit that acquires the second packet from the fabric communication unit and generating a response packet to a request included in the second packet that has been acquired.

Abstract: A communication control device for a subscriber station of a serial bus system. The communication control device has a communication control module for generating a transmitted signal for controlling a communication of the subscriber station with at least one other subscriber station of the bus system, in which bus system at least a first communication phase and a second communication phase are used for exchanging messages between subscriber stations of the bus system, a first terminal for transmitting, in an operating mode of the first communication phase, the transmitted signal to a transmitting/receiving device, a second terminal for receiving, in the operating mode of the first communication phase, a digital received signal from the transmitting/receiving device, and an operating mode switching module for switching the transmission direction of the first and the second terminal in the second communication phase to the same direction for differential signal transmission.

Abstract: Provided are a serial communication device and a serial communication system for a memory access. The serial communication device for a memory access may include: a system-on-chip (SoC) bus interface receiving a request transaction from a hardware acceleration device; a master protocol processor converting a request transaction received through the SoC bus interface into a packet according to a predetermined packet protocol; and a serial transceiver serial-transmitting the packet.