Abstract: A mechanism is provided for storage enclosures to communicate with one another using pre-existing cables allowing the user to dynamically attach different types and speeds of Fiber Channel enclosures together. The mechanism uses a transmit disable line and receive loss of signal line of a small form-factor pluggable optical cable to provide a communication link between enclosures before the Fiber Channel loop is setup and stable. The mechanism on the transmit side pulses the transmit disable line to communicate configuration information. The mechanism on the receive side receives the configuration information on the receive loss of signal line. The transmit disable line and the receive loss of signal line operate as a one-wire communication scheme, providing a communication link to communicate configuration information before the Fiber Channel loop is established.

Abstract: In a method and system for data and signal transfer between different sub-units of a medically-related system, in particular a CT system, digitized signals and digital data are transmitted together on a transmission line by means of serial multiplexing. The digitized signals and the digital data are transferred combined into individual packets having a length that is so small that the adherence to a predetermined updating rate of the signals is achieved. The expenditure for the wiring as well as for future expansions in medically-related systems can be significantly reduced.

Abstract: A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication in accordance with the SATA format with the host. The serial interface during the transmission of primitives in a pass-through phase, inserts pass-through information to the host within or outside of a Frame Information Structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.

Abstract: Method and system for an adapter operationally coupled to a host system and a network is provided. The adapter includes an internal memory that can be configured in a first mode to operate as a dedicated random access memory used by a main processor of the adapter; or configured in a second mode to operate both as a random access memory used by the main processor and also used for storing information received from the network. The method includes enabling the second mode of the internal memory so that the internal memory is configured to operate both as random access memory for the main processor and for storing information received from the network.

Abstract: An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated with the loop during a first iteration of the loop, storing first decoded instruction information associated with the first instruction during the first iteration of the loop, and using the stored first decoded instruction information during at least a second iteration of the loop without further fetching and decoding of the first instruction during the at least a second iteration of the loop.

Abstract: Send queues provided in an InfiniBand hardware adapter receive a single transmission from a connected computer system which includes work request information, address vector, and message data. This information is sufficient for the adapter to generate packet header information and to send the requested message, thereby providing a low latency sending mechanism. The system stores completion information in tables each dedicated to one of the send queues.

Abstract: A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.

Abstract: A processing system includes a communication bus. a controller, an Input/Output (“I/O”) block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electrical communication with the logic segments. A first logic segment communicates to a Second logic segment over the communication bus. Reconfiguration can partition a first logic segment into a second and a third logic segment where the smaller logic segments are in electrical communication with the communication bus. Resources are dynamically reallocated when reconfigurable units are either combined or partitioned. More specifically, both partitioning a logic segment and combining two or more logic segments can change the bus width allocated to a reconfigurable unit and the quantity of logic gates in the reconfigured unit. As a result of a reconfiguration, a logic segment's embedded resources can change.

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip which includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus and is stacked on the first semiconductor chip. A pad region in which pads (electrodes) for connecting the external device and the high-speed serial I/F circuit are disposed is provided along a first side of the second semiconductor chip which is the short side. A pad region in which pads for connecting an internal circuit included in the first semiconductor chip and the high-speed serial I/F circuit are disposed is provided along a second side of the second semiconductor chip which is the long side.

Abstract: There is provided a method, system, and computer program product for extracting information related to a monitored device communicatively coupled to a network using an HTTP communication protocol. The method includes: retrieving, from a first memory, vendor and model information of the monitored device; determining vendor and model through the web page from the monitored device; obtaining the device state information; and storing, in a second memory, the device information obtained in the accessing step, in association with the vendor and model information.

Abstract: A method relating to wireless human interface device (HID) coordination is disclosed. A first human interface device (HID) is wirelessly coupled to two or more computing devices, wherein the first HID is configured to toggle between interactions with each of the two or more computing devices. An inquiry or paging message is broadcast to one or more HIDs, including a second HID wirelessly coupled to the two or more computing devices, wherein the second HID is configured to receive and provide a response to the inquiry or paging message. The second HID is located based on the response to the inquiry or paging message. A wireless link is established between the first HID and the second HID based on the locating, wherein the first HID is configured to coordinate, via the wireless link, interactions with the two or more computing devices by both the first HID and the second HID based on the toggle.

Abstract: Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user command. The user operation filter comprises a queue and a management device. The queue receives and stores a plurality of UOPs, and outputs stored UOPs as control instructions on a first-in-first-out basis. The management device determines whether the queue is full. If the queue is full, the management device discards at least one of the stored UOPs prior to storing the instant UOP in the queue. Each playback management device receives control instructions for controlling corresponding playback devices.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip includes a high-speed serial I/F circuit which transfers serial data between the high-speed serial I/F circuit and an external device through a serial bus, and transfers parallel data between the high-speed serial I/F circuit and an internal circuit included in the first semiconductor chip. A physical layer circuit of the high-speed serial I/F circuit is disposed on a first side of the second semiconductor chip which is the short side, and a logic circuit is disposed on a third side opposite to the first side.

Abstract: The present disclosure relates to attempting to initialize and configure a device utilizing a remote server and, more specifically, to attempting to initialize a device with low level device configuration information that is stored on a remote server or servers.

Abstract: Disclosed are a data processing system and a method of isolating a plurality of input/output adapter units of that system. The data processing system comprises, in addition to the input/output adapter units, a set of processors, a host bridge, and a system bus connecting the set of processors and the host bridge. Each of the input/output adapter units has a respective identifier; and the set of processors send commands to the host bridge, said commands including one or more of the identifiers of the input/output adapter units. In the preferred embodiment, these identifiers are HyperTransport defined Unit IDs, and the commands issued by the set of processors include a Unit ID field including one or more of the Unit IDs of input/output adapters.

Abstract: A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system serial COM port. Data is secured and re-directed to a legacy device via a network port instead of the serial COM port. Conversely, data destined for the host system is provided to a device server via a server COM port by the legacy serial device. The data can be encrypted and sent to the host system via the network. The redirector software module decrypts the encrypted data and presents it to the consumer application as if the data had arrived via the local COM port.

Abstract: The present invention provides a portable electronic storage device able to receive, store, and transmit or otherwise convey digital data and images from one electronic device to another. The storage device may generally include a housing containing one or more electronic components, and a plurality of connectors extending from the housing, the connectors being engageable with secondary electronic devices for the transfer of data and/or images. The electronic storage device may further include a software program operable via the secondary electronic devices for the manipulation of data and/or images.

Abstract: The present invention utilizes a single DMA engine to process the requests of active DMA channels competing for transfer of data over a single bus. The invention employs two identical sets of DMA request registers which are connected to a processor. These register sets are connected through a switching means to the DMA engine. While a first DMA transfer represented by a first set of registers is active, the process enables preparation of the next request in a second set of registers. Upon completion of the first DMA transfer, the DMA engine is switched to commence processing of the DMA request represented by the second set of registers.

Abstract: A data transfer control device, which transfers a large capacity of data speedily and sequentially, has three buffers that are used as a WR (write) buffer, an intermediate buffer, and an RD (read) buffer. To send data sequentially, the data transfer control device switches-over the buffers in one of the following three ways (A), (B), and (C), using determination flags indicating whether the buffers store effective data (data not yet referenced). A buffer control device switches-over (A) the WR buffer and RD buffer if a WR buffer effective flag 33 is on and an intermediate buffer effective flag 34 and an RD buffer effective flag 35 are off, (B) the WR buffer and the intermediate buffer if the WR buffer effective flag 33 and the RD buffer effective flag 35 are on and the intermediate buffer effective flag 34 is off, and (C) the intermediate buffer and the RD buffer if the intermediate buffer effective flag 34 is on and the RD buffer effective flag 35 is off.