Abstract: An electronic device can operate as an external device of an information processing apparatus. The electronic device includes a connecting unit for connecting to the information processing apparatus, a command processor for processing a command sent from the information processing apparatus through the connecting unit, a rechargeable battery, a charging controller for controlling a charging operation of the rechargeable battery, and an operating mode managing unit which, when the connecting unit is connected to an interface having a power-supply function, selects one of a normal operating mode in which the electronic device operates as the external device of the information processing apparatus, and a charging mode in which the electronic device stops operating as the external device of the information processing apparatus and charges the rechargeable battery. The command processor processes the command in accordance with the selected operating mode.

Abstract: Memory resources can be optimized by dynamically determining a threshold value of a storage device used for buffering in accordance with a compression rate of data for streaming reproduction. A data reproduction device for temporarily storing compressed data that is downloaded from a server and sequentially performing the streaming reproduction, wherein the amount of data stored in a HDD is optimized by changing and setting the threshold value in accordance with the compression rate of the compressed data.

Abstract: An input device is provided for capturing handwriting strokes while in a handwriting mode and for providing audio-related functionality. The input device may be formed in the shape of a pen, and may or may not include an ink cartridge to facilitate movement of the input device in a familiar manner. In one configuration, an input device provides verbal messages, such as warnings to a user. In another configuration, an input device receives audible commands and performs related actions. In a further configuration, an input device recognizes specific movements, such as a word traced therewith, and provides audible information based on the movements. Methods for using input devices and computer-readable instructions for performing the methods are also provided.

Abstract: A data output apparatus (a) sets an output terminal to a first state where a data format of the output terminal is locked to a data format indicated by a first command and where the output terminal cannot output video data whose data format is different from the data format indicated by the first command, if the first command is received from a first control device, and (b) sets the output terminal to a second state where the data format of the output terminal is not locked to the data format indicated by the first command and where the output terminal can output video data whose data format is different from the data format indicated by the first command, if the second command is received from a second control device while the data format of the output terminal is locked to the data format indicated by the first command.

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract: Because cable length affects signal quality, amplifying signals differently to account for cable length (“tuning”) becomes especially important when high speed signals are used. Cable length information may be stored in a non-volatile memory which may be integrated into a cable assembly or may be a discrete component between the cable and an interface. Rather than using a dedicated data line to the memory component a ground line may be connected to the memory component and multiplexed. During normal operation the selected line is grounded through a switching device. When a cable is detected, a management controller changes the state of the switching device to decouple the selected line from ground to allow the management controller access to the data stored in the memory component, including cable length information. The selected line is then re-coupled to ground and interface circuits may be tuned for the cable length.

Abstract: A data output apparatus receives a first command from a first device, and receives a second command from a second device. The apparatus (a) sets an output terminal to a locked state where a data format thereof is locked to a data format indicated by the first command and where the terminal cannot output video data whose data format is different, if the first command is received while the terminal is being set to an unlocked state, (b) determines whether a data format indicated by the second command is the same as the data format of the terminal, if the second command is received while the terminal is being set to the locked state, and (c) transmits a response for informing the second device that the second command is accepted, if the data format indicated by the second command is the same as the data format of the terminal.

Abstract: A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.

Abstract: A file is transferred directly between a parent magnetic-disk device and a child magnetic-disk device. In one embodiment, a parent magnetic-disk device has a host-mode execution program, whereas a child magnetic-disk device is capable operating in a device mode as is the case with an ordinary magnetic-disk device. The parent magnetic-disk device has an operating-mode-setting unit including a special-purpose jumper block. An MPU employed in the parent magnetic-disk device executes the host-mode execution program to put the parent magnetic-disk device in a host mode. At an activation time, the MPU refers to the logic of the special jumper block to start an operation in the host mode. The MPU controls the parent magnetic-disk device to directly transfer a file to the child magnetic-disk device. Thus, the file can be transferred between the parent and child magnetic-disk devices without intervention by a host computer.

Abstract: A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch accommodating m bits, e.g., 32 bits; control circuitry for depositing the m bits of data from a data bus port into the staging latch addressed using a specific register address; and control circuitry adapted to merging the m bit data contained in the staging latch with m bit data from a data bus port, to generate the n bit wide data, for example, 64 bits, that is written atomically to a storage array specified by an address corresponding to a storage array location.

Abstract: In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus.

Abstract: A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count associated with the data valid bits; and coupling the count to the first-in first-out memory. The step of generating a count associated with the data valid bits may comprise encoding the data valid bits to generate a valid data word representing the number of pipeline stages having valid data. The method of further comprises a step of generating an almost full signal based upon the count, and in particular generating an almost full signal when a read pointer incremented by the count of valid bits in the pipeline stages equals a write pointer. A circuit for processing data is also disclosed.

Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

Abstract: A reader and writer access a ring buffer without using a locking mechanism, thereby avoiding any delays attendant to using a locking mechanism when performing read operations to supply the reader with data from the ring buffer. Other measures are used to reduce delayed performance of read operations. If data requested by a reader is not available in the ring buffer, rather than waiting until the data becomes available, substitute data not from the ring buffer is provided instead. The ring buffer's size may be dynamically increased or decreased to improve performance of read and write operations and/or to conserve computer resources.

Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.

Abstract: A system including a host and a subsystem operatively coupled to the host and having a flash memory is provided. The host reads device information from a memory and provides a predetermined command to the subsystem that changes the multi-source mode to a host mode responsive to the device information. A method for controlling a subsystem and a host is additionally provided. The method includes reading device information from a memory on the subsystem and determining whether the subsystem operates in a multi-source mode responsive to the device information. The method provides a predetermined command to the subsystem so as to change the multi-source mode to a host mode responsive to the determining.

Abstract: A data processing system and method of isolating a plurality of I/O adapters in the system. The data processing system also comprises a set of processors communicating with the I/O adapters using a PCIe protocol. Each of the I/O adapters has a respective ID. In the preferred embodiment the commands issued by the I/O adapters include a PCIe defined Requestor ID field including one or more of the Requestor IDs of I/O Adapters. The Req IDs can be used as an input to a CAM which provides an index to a TVT to identify a unique and independent system memory space for the I/O adapter.

Abstract: A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

Abstract: A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system adapted to control the physical computer. The computer system further comprises a host executable on the physical computer that manages physical resources coupled to the physical computer on behalf of the virtual machine monitor and the at least one guest operating system. The host is adapted to virtualize a Peripheral Component Interconnect (PCI) configuration address space whereby the at least one guest operating system controls PCI input/output (I/O) devices directly and in absence of I/O emulation.

Abstract: A water heater has a modular control system. The water heater comprises a tank, a heating element, a first controller, and a second controller. The heating element is coupled to the tank. The first controller is mounted on the tank and has a first communication port. The second controller has a second communication port communicatively coupled to the first communication port of the first controller. The first controller is configured to control the heating element in accordance with a first algorithm in an absence of the second controller, and the second controller is configured to control the heating element in accordance with a second algorithm.