Abstract: A host library controller employs a plurality of ports for establishing a plurality of communication paths from the host library controller to a medium changer library. The host library controller further employs a processor and a memory storing instructions for the processor to issue a command from a medium changer command set, and to select one or more of the ports for communicating the medium changer command to the medium changer library depending on a command processing status of each port.

Abstract: A method for automating configuration of devices in a network having a network bus for communicating with the devices, wherein the network is implemented in a physical environment the method comprising detecting a device assembly that is connected to the network bus, wherein the device assembly includes a plurality of devices assembled thereon in a predetermined physical order; upon detecting a device assembly connected to the network bus, determining whether the detected device assembly is of a predetermined first type; upon determining that the detected device assembly is of the first type, reading data from the plurality of devices assembled thereon in an order corresponding to the predetermined physical order of the plurality of devices as assembled on the device assembly; and identifying a physical location in the physical environment of each of the plurality of devices on the first-type device assembly based on the order in which data of the plurality of devices is read from the first-type device assemb

Abstract: There is provided an information processing apparatus in which a CPU and an audio processing unit are coupled by a bus. The audio processing unit includes a ring buffer that temporarily retains audio data, and performs an input/output process of the audio data. An interrupt signal generator generates a buffer empty signal, when the audio data is output from a buffer in the ring buffer and the buffer is empty, decimates the buffer empty signal in accordance with a sampling frequency of audio, and then feeds the interrupt signal that survives the decimation to the CPU. The CPU, upon receiving the buffer empty signal, issues a DMA transfer instruction for writing the audio data into the empty buffer in the ring buffer.

Abstract: An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system. The interrupt controller has inputs for receiving service requests for invoking service routines. The service routines have higher priorities than the tasks executed on the processors. Associated with each processor is a register for storing the priority of the task executing on the processor. A comparator coupled to the processors determines the processor executing the task having a lower priority among the priorities of the tasks executing on the processors. For each service request received, a distributor generates an interrupt request for invoking the service routine of the service request on the processor with the lower priority. The register with the lower priority is set to the higher priority of the service routine in response to the interrupt request. For each processor, the interrupt controller has an output for transmitting the interrupt request to the processor.

Abstract: An apparatus for the remote wireless control of a consumer electronic audio visual appliance such as a TV set, and/or for internet uploading, includes a remote control handset and a wireless receiver for connection to the appliance. The remote control unit is adapted to transmit audio and/or visual data (A/V data) and control codes to the receiver. The receiver is responsive to the A/V data and control codes to control the appliance to play and/or display the A/V data. The remote control unit includes a reader for a storage medium for A/V data, or a cable or wireless interface to an A/V acquisition device such as digital video or digital still camera or digital music player or recorder.

Abstract: A keyboard-mouse-video (KVM) switch has a server interface, a client interface, a switch circuit and a digital video overlapping circuit. The server interface is connected to plural computers, and the client interface is connected to plural sets of manipulation and display devices. The switch circuit routes paths between the computers and the sets of manipulation and display device. The digital video overlapping circuit overlaps a digital video overlapping image onto a digital video signal received from one of the computers through the server interface. The overlapped digital video signal is then transmitted to one of the sets of manipulation and display device through the client interface.

Abstract: A memory registration abstraction layer includes decision logic for dynamic, efficient determination of memory copy versus registration. The exemplary embodiments apply to direct memory access environments. The memory registration abstraction layer also includes tracking logic for monitoring the usage history for certain ranges of memory registration requests. The registration logic chooses to copy memory or map memory based on training and observation of application behavior, taking the more efficient performance path without requiring changes to the application.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A storage control apparatus of the present invention controls the number of multiple commands issued from a host machine without shutting down the host machine. A communication port of the storage control apparatus carries out communications with the hosts in accordance with the iSCSI protocol. Command processing resources are managed for each communication port. A resource allocation control part calculates the number of commands capable of being received on the basis of the remaining amount of command processing resources inside shared port resources, a change in the number of commands received from a host, communication delay time, and the state of execution of a command issued from a host or the like. A MaxCmdSN is calculated by adding the results of command processing by a command execution part and the receivable number calculated by the resource allocation control part to the value of the latest CmdSN received from a host.

Abstract: A device recognition system comprises an identification module of a computer device configured to generate an impedance signature for an external device using an impedance of the external device measured at least two different stimuli, the impedance signature used to identify the external device.

Abstract: A configurable application specific product with a configurable input/output interface is described. The illustrative embodiment of the invention includes a single microcontroller and a microprocessor having a configurable I/O interface that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Abstract: A channel adaptor is provided which can be shared by a plurality of operating systems (OS's) running in a data processing system, by generating an address translation table without changing input/output process control data. A plurality of OS's execute an input/output process for the channel adaptor by using input/output process control data having different identifiers, without sharing the input/output process control data for the channel adaptor by different OS's. The data processing system generates one virtual address translation table from a plurality of address translation tables generated by OS's, and the channel adaptor processes the input/output control data of OS's by using the virtual address translation table.

Abstract: Methods and associated structure to assure correct order in delivery of SATA frames over a SAS wide port. In one aspect hereof, new connection requests from a SATA device are rejected until prior frames residing in receive buffers of the SAS/SATA controller are properly processed. In another aspect, when a device is already connected to the controller, the SAS/SATA controller may prevent return of a receiver ready primitive in response to a transmitter ready primitive until previously received frames are removed from the receive buffers.

Abstract: A device determines whether a speed mode between the device and an external device is a first speed mode or a second speed mode, communicates with the external device at first speed if the speed mode is the first speed mode, and communicates with the external device at second speed slower than the first speed if the speed mode is the second speed mode. The device enables transfer of image data and displays the image data being transferred to the external device, if the speed mode is the first speed mode. The device disables the transfer of the image data and stops displaying the image data, if the speed mode is the second speed mode.

Abstract: A method and apparatus for managing task context are provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.

Abstract: An input/output device stores host status information about the status of a host, and controls the input/output of data. By referring to the input/output information and the host status information, the device performs optimization control of selecting notification either by an interrupt process or a non-interrupt process. When a notification by the interrupt process is selected, data transfer control is performed to the host, and the data is transferred to the host by an interrupt. When a notification by the non-interrupt process is selected, data transfer control is performed to the host, and notification control is performed to transfer the data to the host by polling.

Abstract: The present invention is a system for providing Multiple Independent Levels of Security (MILS) partitioning. The system includes a memory, a bus controller communicatively coupled to the memory via a memory bus, and a MILS controller communicatively coupled to the bus controller via a host-side bus, the MILS controller configured for monitoring and controlling system transactions. The system further includes a plurality of input/output (I/O) devices communicatively coupled to the MILS controller via a plurality of corresponding device-side buses. The system further includes a MILS separation kernel configured for mapping regions of the memory to a plurality of user partitions. Each I/O device included in the plurality of I/O devices is allocated to a partition included in the plurality of partitions and is isolated from MILS separation kernel space. The MILS separation kernel is configured for guaranteeing isolation of the partitions of the memory.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Abstract: A method for programming programmable devices includes monitoring a status pin for each of the programmable devices, maintaining state information for the programmable devices indicating whether each programmable device is programmed, and transitioning each programmable device from a programmed state to an operating state. A monitoring module includes detectors, a memory and a processor. The detectors detect indications on the status pins of programmable devices that the programmable devices are programmed. The memory stores state information about the programmable devices. The processor communicates control signals to the programmable devices instructing them to transition from the programmed state to the operating state.