Abstract: A flash memory and a method for utilizing the same are disclosed. The method for utilizing a flash memory includes the steps of: a) providing a flash memory of a single chip; b) formatting the flash memory and marking bad blocks of the flash memory as a bad-block area free of reliably saved data; c) calculating a capacity of an available memory with the flash memory, wherein the available memory excludes the bad-block area of the flash memory; and d) dividing the available memory into a first storing memory and a second storing memory, wherein the first storing memory and the second storing memory have different capacities.

Abstract: A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a respective one of the plurality of registers and a corresponding processor mode. The input ports receive inputs for addressing at least one register using an encoded address. The output ports output data from at least register addressable by an encoded address.

Abstract: A method for improving storage system performance is disclosed. The method includes cloning information stored in a first unit of storage in a second unit of storage. The first unit of storage is stored in a first cache maintained by an upper-level system, while the second unit of storage is stored in a second cache.

Abstract: Techniques are provided for performing a copy operation. An instant virtual copy operation is issued from a first portion of data to a primary mirroring portion of data, wherein the primary mirroring portion of data corresponds to a secondary mirroring portion of data, and wherein the primary mirroring portion of data and the secondary mirroring portion of data are in a mirroring relationship. The mirroring relationship is transitioned to a duplex pending state in response to determining that the mirroring relationship is in a full duplex state. When the mirroring relationship is in a duplex pending state, each block of data involved in the instant virtual copy operation is transferred from the primary mirroring portion of data to the secondary mirroring portion of data.

Abstract: In the information process device 1, only when it is determined that the password rewritten in the change password memory area 14a of the backup RAM 14 and the password rewritten in the change password memory area 31a of the second flash memory 31 coincide with each other (S202: YES), the menu display of the liquid crystal display 21 is conducted (S107) and it is permitted to start execution of the application program (S123) based on that the menu M2 of “2. start of game” is selected in the menu display. Further, based on that the menu M1 of “1. set of password” is selected in the menu display (S109: 1), it is permitted input of the change password by touching each of the areas 22c to 22n of the transparent touch panel 22 (S112).

Abstract: Described is a technology by which a new volume or partition may be created on a disk, e.g., by running a shrink program and then reclaiming freed space. Shrink occurs online, while the user or system processes may be otherwise using the disk for reads and writes. Further, the technology operates while protecting snapshot versions of the volume. To shrink, upon receiving a request to shrink a volume to within a boundary, new allocations are restricted such that any allocation is to a volume area within the boundary. Data is moved from outside the boundary to within the boundary, and the shrink is committed when no volume data remains outside the boundary. A reduced-size volume or partition that does not include the specified region is committed when the data has been moved out of the specified region. A new volume or partition may be freed that corresponds to the region.

Abstract: A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size that is determined by area size information included in the area allocation request is searched for as a candidate area on the basis of a memory management table 400. And overlap flag corresponding to an adjoining area that is contiguous with the candidate area in its lower address orientation is read from the memory management table 400, and, based on the overlap flag, it is determined whether or not the adjoining area is an area that allows overlapped allocation. If it is determined the area is an area allowing overlapped allocation, a used area that overlaps with the adjoining area is allocated.

Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.

Abstract: In an embodiment, a method for an adaptive address space operating system, includes: selecting a first model of the address space layout for a process; attempting to perform an operation within a virtual address; determining if the operation can be performed successfully based on the first model or based upon a second model; if the operation cannot be performed successfully based upon the first model but can be performed successfully based upon the second model, then converting the address space layout from the first model to the second model; and performing the operation.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

Abstract: A method of managing memory mapped input/output (I/O) for a run-time environment is disclosed, in which opaque references are used for accessing information blocks included in files used in a dynamic run-time environment. The information block is stored in a shared memory space of pages that are each aligned on respective boundaries having addresses that are each some multiple of two raised to an integer power. The opaque reference used for the dynamic run-time environment includes at least an index, or page number reference into a page map of references to the pages of the shared memory space, and an offset value indicating an offset into the referenced page for the beginning of the storage of the information block. Control bits of the opaque reference indicate information such as the mapping mode, e.g., read-only, read-write, or private. Pages which are modified by a process may be written back to a backing store of the file based on control bits which indicate that a page has been modified.

Abstract: In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.

Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: A burden placed on an administrator in creating a volume is reduced. An evaluation hint value and a performance hint value are employed as hint values for each hint. The evaluation hint value is determined by the administrator considering a service usage and the like of the service server 1 to which the volume is allocated. The performance hint value is used to determine a performance and a setting of the volume to be created in the storage system 3. The management server 2 has a conversion table indicating a correspondence between the evaluation hint value defined considering the hardware configuration and the performance hint value, with respect to each storage system 3. The management server 2 converts the evaluation hint value designated by the administrator to a performance hint value, by use of the conversion table associated with the storage system to which the volume is to be created, and the management server creates the volume in the storage system 3 according to the performance value.

Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.

Abstract: In a computer system where a site including a storage device system connected to high-rank apparatuses, via a network such as a SAN, and a site including a storage device system similarly connected to high-rank apparatuses via a network are connected to each other via an inter-high-rank-apparatuses network, arbitration-emulation software is installed in each of the high-rank apparatuses. Here, the following two-step arbitration is carried out, thereby determining one high-rank apparatus. Namely, at first, a shared/exclusive control using an already-existing shared volume is performed based on an in-site arbitration within the site. Next, a shared/exclusive control based on an inter-sites arbitration is performed by high-rank apparatuses each of which has won the arbitration within each site.

Abstract: Systems and methods which provide automatic management of cached content are disclosed. These systems and methods may provide a cache manager which is capable of updating content in a cache without receiving a request from a user. Content may be stored in a cache along with associated metadata. Based upon this metadata, the request which resulted in a particular piece of cached content may be regenerated. This regenerated request can be dynamically evaluated and content responsive generated. This newly generated content can be used to replace the previously cached content. Using these systems and methods content in a cache can be automatically managed and dynamically updated.

Abstract: In accordance with the teaching described herein, systems and methods are provided for managing memory space in a mobile device. A plurality of data storage locations may be included. A plurality of software applications may be included, with each software application being operable to store data to a different data storage location. A data store management system may be operable to access and delete data stored in the plurality of data storage locations. If insufficient memory space is available in one of the data storage locations, then the data store management system may access the one data storage location and at least one other data storage location and delete data from at least one of the accessed data storage locations.