Abstract: A system for creating and tracking intelligent unique identifications for memory devices is disclosed. Each memory device includes stored configuration information having a plurality of fields. A storage operating system selectively creates an intelligent unique identification for each memory device in the storage system using the fields in the stored configuration information. The intelligent unique identification may then be stored for tracking and later retrieval.

Abstract: Methods and apparatus for allowing different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one aspect of the present invention, a method for mapping a plurality of logical blocks to a physical block includes identifying a first logical block meets at least one criterion. The method also includes identifying a second logical block which is substantially complementary to the first logical block, and providing contents associated with the first logical block and contents associated with the second logical block to the physical block.

Abstract: A computing system may comprise a processor and a memory controller hub coupled by an external bus such as the front side bus. The processor may also comprise a cache. The processor may operate in SMM and the memory coupled to the memory controller hub may comprise SMM spaces such as compatible, HSEG, and TSEG areas. A software-based attack may write malicious instructions into the cache at an address corresponding to the SMM spaces. The illegal processor memory accesses that occur entirely inside the processor caches due to the cache attack may be forced to occur on the external bus. The memory controller hub may be capable of handling the memory accesses occurring on the external bus thus, protecting the SMM spaces against cache attack.

Abstract: A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data buses for communicating data signals between said memory controller and a respective one of said memory devices, each of said data buses providing a dedicated data signal path to a different one of said memory devices, address interface circuitry for connecting to a common address bus for communicating address signals to each of said memory devices on a shared address signal path, address signals which are directed to different ones of said memory devices being time division multiplexed together on said common address bus, and device selecting circuitry for generating one or more device selecting signals synchronised with said time division multiplexing of said common address bus to select that memory device to which address signals currently asser

Abstract: In one embodiment, a method is provided. The method of this embodiment provides determining if a management queue can be created, and if a management queue can be created, allocating virtually contiguous memory to a management queue associated with a device, registering the management queue, and creating a management queue context.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: There are disclosed systems, computer program products, and methods for self-tuning memory. In an embodiment, a method for self-tuning memory comprises setting a tuning interval and a target range for free memory for a memory pool. If memory consumption falls outside of the set target range for free memory during a tuning interval, a new target size for the memory pool is set based on the target range for free memory. Memory allocation for the memory pool is increased or decreased for the next tuning interval, such that the new target size for the memory pool is reached. A decrement rate may be used to provide a controlled decrease of the memory pool over a plurality of tuning intervals if necessary, until the new target size for the memory pool is reached.

Abstract: Described are techniques for overriding an existing device reservation. Discovery processing is performed by a first data storage system to locate a specified device. The discovery processing includes determining whether there is a reservation conflict for said device of a second data storage system. If there is a reservation conflict for the device, a command is issued from the first data storage system to the second data storage system during said discovery processing to create an override for said reservation conflict. The override causes processing to be performed at a subsequent point in time so that an existing reservation associated with the reservation conflict is overridden in connection with performing a first process on said first data storage system.

Abstract: A method for caching data may be practiced, for example, in a computing environment including a server system that provides data to client systems. The server system includes a number of caches for storing data. The method allows a least expensive cache to first cache data or return data requested by a client. The method includes receiving data to be cached at a cache. The method further includes determining that the data has not been previously cached at a preceding cache. If the data has not been previously cached at a preceding cache the data is cached at the cache. Alternatively, requests for data may be received at a first cache. If the data is at the first cache, the first cache returns the data. If the data is not at the first cache, the request for data is forwarded to a subsequent cache.

Abstract: In a nonvolatile memory system, a host allocates clusters and records allocation information in a File Allocation Table that is stored in the nonvolatile memory. A controller separately allocates certain data and records allocation in a record in a volatile memory. File Allocation Table information provided to the host is modified according to the record in the volatile memory.

Abstract: An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node including the first cache and assigning a modified cache state to the cache data block in response to initiating the first store operation. The method may further include evicting the cache data block from the first cache subsequent to initiating the first store operation, storing the cache data block in a remote cache in response to the evicting, and assigning a remote directory state to a coherence directory entry corresponding to the cache data block in response to storing the cache data block in the remote cache, where the remote directory state is distinct from an invalid directory state.

Abstract: A method of monitoring runtime memory usage by a program. The method can include retrieving data from a first region of virtual memory that has been allocated to the program and compressing the data. A data compression rate can be measured. The method further can include generating a notification comprising notification data indicating that the first region of memory was not efficiently used by the program during execution when the data compression exceeds a threshold value or the data compression rate exceeds a statistical value determined from an application's memory usage.

Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Abstract: A method, for determining sufficiency of a given set of portions included within a storage system (SS) to accommodate one or more flows of data anticipated as flowing therethrough, may include: configuring the given set to include at least one of following portions, a given stable of one or more providers of data-storage (PDSs), and an SS-infrastructure; identifying components within members of the given set as queuing centers according to the one or more flows, respectively; estimating one or more capacity values, based upon the one or more flows, that will be demanded of the components, respectively; and determining whether the estimated one or more capacity values are acceptable in a context of corresponding capacity values attributed to the components, respectively.

Abstract: A composite machine performs various types of image processing with executing relevant applications, wherein: upon starting an application stored in a hard disk drive, predetermined diagnosis processing is performed on the hard disk drive beforehand; and, upon starting an application stored in a flash memory, the application is startable independently from the predetermined diagnosis processing being performed on the hard disk drive.

Abstract: An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).

Abstract: According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system, having a non-volatile memory, wherein data is written to the non-volatile memory in the form of at least one logical sector the method comprising: monitoring the logical sector data which is to be written to the non-volatile memory, detecting the presence of a pattern in the logical sector data, upon detecting a repetitive pattern recording the repetitive pattern of the logical sector in a sector address table in the non-volatile memory without making a record of the logical sector data in the non- volatile memory.

Abstract: A processing device includes an optimizer to migrate objects from an external memory of a network processing to local memory device to registers connected to a processor. The optimizer further aligns and eliminates redundant unitialization code of the objects.