Abstract: A flash memory based processing apparatus including, among other things, an integrated controller to authenticate various operations, such as read, write, patch, and key operations, and directly control read access to partitions of the memory array of the flash device via operations in various read access modes. Other embodiments may be described and claimed herein.

Abstract: Systems, methods, apparatus and software can combine information about host access to virtualization functionality and virtualization functionality access to storage, use this information in decisions pertaining to high availability of virtualization in an SAN. Upon detection of the partitioning of a SAN fabric, accessibility information is gathered. That information is analyzed to uncover potential failover scenarios, orchestrate such failovers, and in some cases select best case solutions from among several possible solutions based on access prioritization criteria (e.g., defined priority, maximum access, maximum I/O, etc.).

Abstract: A computer is modified to add a memory management module between a memory controller and memory. The module may control or intercept signals between the memory controller and the memory to disable a portion or all of the computer's normal function. The memory management module may be a discrete device or may be part of the memory controller itself.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: Resolving retention policy conflicts is disclosed. An indication is received that two or more retention policies apply to an item of content. A merged retention policy that is based at least in part on the respective requirements of the two or more retention policies is generated automatically for the item of content.

Abstract: Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.

Abstract: A method and system for accessing a non-volatile memory is disclosed. The method includes writing a first stream of data to a first block of a first region of a non-volatile memory and detecting a full condition of the first block of the first region. Further, the method includes identifying data to be copied from the first block of the first region and copying the identified data from the first block of the first region to a second block of the first region of the non-volatile memory. The method also includes writing a second stream of data to the second block of the first region and writing a third stream of data to a first block of a second region of the non-volatile memory. In addition, the method includes detecting a full condition of the first block of the second region, identifying data to be copied from the first block of the second region and copying the identified data from the first block of the second region to a second block of the second region of the non-volatile memory.

Abstract: An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the base unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.

Abstract: A storing-reproducing unit 200 recognizes a free space of a contents storage area by a storage-area-administrating device, sets a recording timing duration based on the recognized free space of the contents storage area, and selects a schedule information of a contents to be recorded from recording schedule list information. Hence, frequency of storing the contents in the HDD 270 can be reduced, thereby avoiding that the contents which has not yet watched is erased by self-erasing, so that the contents can be effectively recorded. Therefore, a user can secure flexibility in time in watching the contents.

Abstract: A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by an encoded address, wherein the encoded address corresponds to at least one register and processor mode. The input ports receive inputs for addressing at least one memory location using an encoded address. The output ports output data from at least memory location addressable by an encoded address.

Abstract: Various systems and methods for maintaining write order fidelity in a distributed environment are disclosed. One method, which can be performed by each node in a cluster, involves associating a current sequence number with each of several write operations included in a set of independent write operations. In response to detecting that one of the write operations in the set is ready to complete, a new sequence number is selected, and that new sequence number is thereafter used as the current sequence number. None of write operations in the set is allowed to return to the application that initiated the write operations until the new sequence number has been advertised to each other node in the cluster. The method also involves receiving a message advertising a first sequence number from another node in the cluster, and subsequently using the first sequence number as the current sequence number.

Abstract: A data processing system comprises a processor to process instructions. A plurality of pipeline stages to execute instructions including a register file. The register file includes a memory unit having a plurality of memory locations, each memory location being addressable by an encoded address. The encoded address corresponds to at least one register and processing mode. Input ports receive inputs for addressing at least one of the memory locations using an encoded address. Output ports to output data from at least one of the memory locations using an encoded address.

Abstract: Methods and apparatus are provided for efficiently selecting virtualization engines in storage area networks. Initiators, targets, and candidate virtualization engines associated with a virtual logical unit number (VLUN) are identified and characteristics such as latency, network topology, load, and mirroring and striping characteristics are analyzed and used to efficiently select a virtualization engine for a particular VLUN in a storage area network. A virtualization engine can be implemented in a line card associated with a fibre channel switch.

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: An apparatus, system, and method are disclosed for global metadata copy repair. The apparatus includes a control module for copying global metadata from primary storage to target storage, a verification module configured to identify invalid track in the global metadata, a location module configured to maintain a current read address, and a read module configured to find a valid copy of the invalid track. The system includes a plurality of hosts, a storage controller in communication with the plurality of hosts over a network, a primary storage device, a target storage device, and the apparatus. The method includes copying global metadata from a primary storage device to a target storage device, identifying invalid track in the global metadata of the primary storage device, maintaining a current read address of a buffer read, and finding a valid copy of the invalid track.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.

Abstract: A RAID disk array controller implements a write mask to support partial-stripe updates from a host system without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host is transferred into a single buffer and a local processor tracks—by setting bits in the write mask—which segments of the target stripe are updated. The disk array is accessed to transfer the target stripe into the same buffer, but the buffer memory write enable is inhibited—responsive to the write mask—during transfer of the segments that were updated by the host. The complete, updated stripe is thus formed in a single buffer for parity calculations and write to the disk array.

Abstract: A computer implemented hierarchical method for paging data, when evicting a page of data from the computer system main storage, evicting the page to a first paging store (preferably NVRAM). When evicting a page of data from the first paging store, evicting the page to a second paging store (such as a disk). When the main store requires a page of data that is not in the main store and when the page of data is available in the first paging store, loading the third page of data into main store from first paging store. When the page of data is not available in the first paging store, loading the third page of data into main store from the second store. Optionally, pages of main store are saved and restored from NVRAM during a power-down, power-up sequence of events.

Abstract: A flash driver architecture openly compatible to operate as interface between most types of file systems and flash memory media regardless of the manufacturer. The flash driver includes a flash abstraction logic that serves as a manager for operating characteristics that are common to the plurality of different types flash memory media. The flash driver may also include a programmable flash medium logic that performs more specific operations in direct communication with the flash memory medium. A user/manufacturer of a computer device can optimally select a set of programmable entry points associated with the flash medium logic to ensure congruent and seamless operation between the file system and flash memory medium selected by the user/manufacturer of the computer.