Patents Examined by Hetul Patel
  • Patent number: 7529908
    Abstract: A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 5, 2009
    Assignee: Cisco Technology, INc.
    Inventors: Harish R. Devanagondi, Rajesh Patil, Sanjeev Mahalawat, Jianyong Sun
  • Patent number: 7516292
    Abstract: Measurement/analysis unit in a Java virtual machine has the function of measuring data when an event of garbage collection occurs, and the function of periodically measuring data. The measurement/analysis unit analyzes the measured data and predicts a danger of a memory shortage, and predicts a danger using an algorithm depending on the type of garbage collection used by the Java virtual machine. An application server is notified of a warning of the predicted danger of a memory shortage by an analysis result notification means by an inter-process communication, or the like. The measurement/analysis unit calculates a memory capacity required to avoid the predicted danger of a memory shortage, and the calculated memory capacity is transmitted to the application server by the analysis result notification means by an inter-process communication, or the like in the same way as the warning.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Limited
    Inventors: Yukihiro Kimura, Masakazu Hayashi, Katsutomo Sekiguchi
  • Patent number: 7509452
    Abstract: An image forming apparatus includes a plurality of erase information each showing whether or not to erase data for each of a plurality of divided areas into which the hard disk is divided, group erase information showing groups grouping the erase information, and erase count information determined based on the group erase information. Based on the erase count information whether or not there is a divided area to erase, the divided area is erased.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: March 24, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Yasuhiro Hattori, Ken Satoh, Hidenori Shindoh, Takahiro Yamazaki
  • Patent number: 7506125
    Abstract: Information terminal and information sharing method are provided which consider survival time of contents at a transmission destination and propagate the contents widely so as to be suitable for contents sharing. In the information terminal and information sharing method, contents allotted with survival time is received, the survival time allotted to the contents is changed, contents allotted with the changed survival time is transmitted to a different information terminal, and the contents is deleted after the changed survival time has expired.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 17, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Yamamoto, Shigeto Oeda
  • Patent number: 7502892
    Abstract: Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache line may be updated if, based on the tag, the cache line is determined to be in a modified or exclusive state.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Per H. Hammarlund, Hermann W. Gartler
  • Patent number: 7502903
    Abstract: A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes determining if a region move will create excessive load so the data storage system appears offline to the host. If not, the method includes causing writes to the source LD region to be mirrored to the target LD region, causing data in the source LD region to be copied to the target LD region, blocking reads and writes to the data storage system, and flushing dirty cache in the data storage system. If flushing the dirty cache is fast so the data storage system appears online to the host, the method includes updating mappings of the virtual volume to the LD regions and resuming the reads and writes to the data storage system.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: March 10, 2009
    Assignee: 3PAR, Inc.
    Inventors: Sushil Thomas, Ashok Singhal
  • Patent number: 7493466
    Abstract: A first storage controller has a multilayer memory hierarchy constructed by LDEV (logical device) connected from LUN, and VDEV (virtual device) connected to the lower order of the LDEV. At least one of the VDEVs is constructed by mapping the memory resources arranged in external storage controllers. The functions of a stripe, RAID, etc. can be added in the mapping. Various kinds of functions (remote copy, variable volume function, etc.) applicable to the normal internal volume can be also used in a virtual internal volume by using the external memory resource as the virtual internal memory resource so that the degree of freedom of utilization is raised.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: February 17, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Keishi Tamura, Shinichi Nakayama, Katsuhiro Uchiumi
  • Patent number: 7478203
    Abstract: A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the new data and associated old data bytes of the old data are different. The new data bytes are then written to the on-chip store. When updating an off-chip store, only the new data bytes that are different are written to the off-chip store. In this manner, off-chip bandwidth requirements for a processor may be reduced.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: January 13, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Paul Caprioli, Shailender Chaudhry
  • Patent number: 7472238
    Abstract: In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a threshold set in the storage retention criteria has been exceeded in an electronic information storage system that stores electronic information on storage media in accordance with a storage retention criteria is provided. The method includes storing a record in a memory associated with a system manager that assigns the storage retention criteria to the certain electronic data, designating the storage media available for overwrite after the threshold set in the storage retention policy has been exceeded, identifying the certain storage media available for overwrite, and retrieving information from the certain media after the threshold set in the storage retention policy has been exceeded.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: December 30, 2008
    Assignee: CommVault Systems, Inc.
    Inventors: Parag Gokhale, Jun Lu, Yanhui Lu, Yu Wang, Rajiv Kottomtharayil
  • Patent number: 7472232
    Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: December 30, 2008
    Assignee: VIA Technologies Inc.
    Inventors: Andrew Su, Jiin Lai, Chad Tsai
  • Patent number: 7469329
    Abstract: There are disclosed methods for dynamically resizing memory pools used by database management systems. In one aspect, if a decrease in allocation to the memory pool is required, at least one page grouping that may be freed from the memory pool is identified as a candidate based on its position in a list of page groupings. If the page grouping contains any used memory blocks, the used memory blocks may be copied from a candidate page grouping to another page grouping in the list in order to free the candidate page grouping. Once the candidate page grouping is free of used memory blocks, the candidate page grouping may be freed from the memory pool. As an example, this method may be used for dynamically resizing locklists or lock memory.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Wojciech Kuczynski, Adam J. Storm, Roger Luo Quan Zheng, Sarah Posner, Christian Marcelo Garcia-Arellano, Sam Sampson Lightstone
  • Patent number: 7464250
    Abstract: The invention discloses a method for loading data from a disk. The method may comprise comparing a current sequence of disk requests to data indicative of a previous disk request sequence. Responsive to detecting a match between the current disk sequence and the previous disk I/O sequence, a copy of data blocks accessed during the current disk sequence may be stored in a contiguous portion of the disk. Responsive to a subsequent request for data in the disk sequence, the request may be mapped to and serviced from the sequential portion of the disk: The continuous portion of the disk to which the data is copied may be on a different partition of the disk than a disk partition on which the original data is stored. A sequence of disk accesses may be recorded. Responsive to retrieving data from the continuous portion, additional data from the contiguous portion of the disk may be prefetched and may be cached in a buffer.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: December 9, 2008
    Assignee: International Business Machines Corporation
    Inventors: Richard Alan Dayan, James Franklin Macon, Jr.
  • Patent number: 7457929
    Abstract: It is an object of the present invention to conduct data transfer or data copying between a plurality of storage systems, without affecting the host computer of the storage systems. Two or more auxiliary storage systems 100B, 100C are connected to a primary storage system 100A connected to a host device 180. The auxiliary storage systems 100B, 100C read journals of data update from the primary storage system 100A at respective independent timings, save the journals in prescribed logical volumes JNL 2, JNL 3, produce copying of the data present in the primary storage system 100A based on the journals present in the logical volumes JNL 2, JNL 3 at the independent timings, and save the copies in auxiliary logical volumes COPY 1, COPY 3. The primary storage system 100A holds the journals till both auxiliary storage systems 100B, 100C read the journals and restore. The timing of journal read can be controlled according to the journal quantity, processing load, and the like.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 25, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Naohisa Kasako
  • Patent number: 7457916
    Abstract: In a storage system having a plurality of disk array devices connected through a network to a host for running an application, and a management server for monitoring the disk array devices, the disk array device includes a physical disk error detecting unit for detecting an error in a physical disk. Meanwhile, the management server stores a corresponding relationship among the application, a logical volume used by the application, and the physical disk corresponding to the logical volume. Moreover, the management server includes an application detecting unit for detecting the application using the logical volume corresponding to the physical disk with the error according to the corresponding relationship when the physical disk error detecting unit of the disk array device detects the error in the physical disk.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: November 25, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Katsuyoshi Suzuki, Toshimitsu Kamano, Kenji Muraoka
  • Patent number: 7454590
    Abstract: In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: November 18, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Paul J. Jordan, Manish K. Shah, Gregory F. Grohoski
  • Patent number: 7454579
    Abstract: Managing access to a shared resource includes receiving a request indicating that an operation requires access to the shared resource, associating the operation with a lock in a lock queue that is associated with the shared resource, and determining whether the shared resource is accessible to the operation.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 18, 2008
    Assignee: EMC Corporation
    Inventor: Daniel Ravan
  • Patent number: 7444489
    Abstract: A method is provided for a data storage system to change the RAID type, the layout characteristics, and the performance characteristics of a virtual volume mapped to logical disk regions in one or more logical disks while the data storage system remains online to a host. Another method is provided for a data storage system to consolidate space in one or more logical disks mapped to a virtual volume while the data storage system remains online to a host. The one or more logical disks can be consolidated to free unused chunklet regions for use in other logical disks.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: October 28, 2008
    Assignee: 3Par, Inc.
    Inventors: Sushil Thomas, Ashok Singhal
  • Patent number: 7444467
    Abstract: A storage system, coupled to a host computer, including at least one controller receiving data from the host computer, and a plurality of memory units connected to the controller. The controller generates parity data and sends the data and the parity data to the memory units. The memory units include a semiconductor memory device which stores the data and the parity data permanently.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: October 28, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
  • Patent number: 7441096
    Abstract: A hierarchical storage system comprises a host computer and a storage system. The storage system comprises at lease two kinds of storage devices, a first tier storage and a second tier storage. The first tier storage is a high performance (or high cost) storage device, and the second tier storage is a lower performance (or lower cost) storage device. The storage system creates a virtual volume based on the first and second tier storages, and enables the host computer to access the virtual volume. A file system in the host computer knows which region of the virtual volume corresponds to the first tier storage and which region of the virtual volume corresponds to the second tier storage. When the file system receives a command to migrate a file from the first tier to the second tier storage, e.g., from a user, the file system examines the address information of the virtual volume where the file resides, and instructs the storage system to migrate the blocks of the designated addresses.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: October 21, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Manabu Kitamura
  • Patent number: 7441095
    Abstract: A first storage controller has a multilayer memory hierarchy constructed by LDEV (logical device) connected from LUN, and VDEV (virtual device) connected to the lower order of the LDEV. At least one of the VDEVs is constructed by mapping the memory resources arranged in external storage controllers. The functions of a stripe, RAID, etc. can be added in the mapping. Various kinds of functions (remote copy, variable volume function, etc.) applicable to the normal internal volume can be also used in a virtual internal volume by using the external memory resource as the virtual internal memory resource so that the degree of freedom of utilization is raised.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: October 21, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Keishi Tamura, Shinichi Nakayama, Katsuhiro Uchiumi