Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: A method and apparatus for storing and retrieving data. The embodiment may maintain all previously-written data in a portion of a storage device, such as a hard disk, writable optical media, or memory, for an indefinite period. Old data is not overwritten unless the storage capacity of the storage device is exceeded. Accordingly, prior versions of data may be accessed by the embodiment as desired.

Abstract: An extensible fingerprint comprised of an ordered list of fingerprints generated by applying each of a plurality of distinct fingerprinting functions to the content of a data item. The extensible fingerprint can be extended by using a new fingerprinting function to compute a new fingerprint and adding the new fingerprint to the list so that the old extensible fingerprint of a data item is used as a prefix of the new extensible fingerprint for that data item. Thus, the fingerprint can be incrementally extended over time. A content-addressed storage system uses extensible fingerprints as addresses and can also change over time.

Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: A data collection management system comprises collection logic configured to store incoming data in a memory at a collection rate, and memory management logic configured to automatically downsample at least a portion of the stored data in response to a usage level of the memory reaching a threshold.

Abstract: Hierarchically paging data in a computer system wherein, when evicting a page of data from the computer system main storage, evicting the page to a first paging store (preferably NVRAM). When evicting a page of data from the first paging store, evicting the page to a second paging store (such as a disk). When the main store requires a page of data that is not in the main store and when the page of data is available in the first paging store, loading the third page of data into main store from first paging store. When the page of data is not available in the first paging store, loading the third page of data into main store from the second store. Optionally, pages of main store are saved and restored from NVRAM during a power-down, power-up sequence of events.

Abstract: It is an object of the present invention to conduct data transfer or data copying between a plurality of storage systems, without affecting the host computer of the storage systems. Two or more auxiliary storage systems 100B, 100C are connected to a primary storage system 100A connected to a host device 180. The auxiliary storage systems 100B, 100C read journals of data update from the primary storage system 100A at respective independent timings, save the journals in prescribed logical volumes JNL 2, JNL 3, produce copying of the data present in the primary storage system 100A based on the journals present in the logical volumes JNL 2, JNL 3 at the independent timings, and save the copies in auxiliary logical volumes COPY 1, COPY 3. The primary storage system 100A holds the journals till both auxiliary storage systems 100B, 100C read the journals and restore. The timing of journal read can be controlled according to the journal quantity, processing load, and the like.

Abstract: Systems and methods for optimizing random access retrieval of a requested data item in a radio frequency identification (RFID) tag are provided. During random access retrieval, a first read of a memory bank in the RFID tag is performed. The first read providers a set of identifier indices stored in a packed object in the memory bank of the RFID tag and a length of the packed object. A determination is then made whether a retrieved identifier index represents the requested data item to be retrieved. A second read of the memory bank, accessing the portion of the memory bank including the data items, is then performed. The location of the data item in the packed object may optionally be determined prior to the second read.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Abstract: Systems and methods for managing cached content are disclosed. More particularly, embodiments of the present invention may allow cached content to be updated (e.g. regenerated or replaced) based on newly added or changed content. Specifically, embodiments of the present invention may allow cached content to be regenerated, replaced or updated based on newly added or changed content associated with the cached content allowing cached content to be updated substantially immediately when pertinent new content is added or content from which the cached content was generated is altered.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node and initiating a first load operation to said cache data block from a second processing node subsequent to initiating said first store operation; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation. The method may further include initiating a second store operation to said cache data block from said second processing node subsequent to initiating said first load operation; and assigning a migratory directory state to said coherence directory entry in response to initiating said second store operation, where the migratory directory state is distinct from a modified directory state.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node; assigning a modified cache state to said cache data block in response to initiating said first store operation. The method may further include initiating a first load operation to said cache data block from a second processing node; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation, where the pairwise-shared directory state is distinct from a shared directory state.

Abstract: Methods and systems are provided for minimizing disruptions when host data on a source logical unit is migrated onto a target logical unit. I/O requests are managed in a particular order during various states of the migration. After the target logical unit is synchronized with the source logical unit and before a commitment to the target logical unit is made, the target logical unit can be evaluated. At that point, the migration can be aborted. During the evaluation of the target logical unit, I/O requests that were directed to the source logical unit are redirected to the target logical unit and I/O requests that were directed to the target logical unit are redirected to the source logical unit. The disclosed methods and systems are equally effective at enabling less disruptive virtualization of a source logical unit as a target logical unit.

Abstract: Circuits, methods, and apparatus that pre-load data that may be needed by a graphics processor to render upcoming scenes. One example determines one or more possible upcoming scenes or views. To save computing resources, the possible upcoming scenes are not fully rendered, but the addresses, and corresponding pages, of data that would be needed to render the scenes are determined. Page usage information is also gathered. Pages that would be needed to render the upcoming scenes, but which are not resident in memory, are read in from a disk drive and stored in memory before they are needed. Pages that are infrequently used are removed from physical memory. In this way, when the scene changes, a large number of page faults do not occur in one frame, rather, they are distributed among several frames.

Abstract: A technique provides access to data in a data storage system. The technique involves providing a disk mirroring assembly including a primary mirror and a secondary mirror. The primary mirror has a set of high speed disk drives. Each high speed disk drive is configured to provide data access while rotating platters at a predefined high performance speed. The secondary mirror has a set of moderate speed disk drives. Each moderate speed disk drive is configured to provide data access while rotating platters at a predefined moderate speed which is less than the predefined high performance speed. The technique further involves operating the disk mirroring assembly in a particular power management state, and performing data access operations on the disk mirroring assembly while the disk mirroring assembly operates in the particular power management state.

Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Abstract: A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting an overflow condition of running out of journal space and recovering the journal space.

Abstract: In a computer system where a site including a storage device system connected to high-rank apparatuses, via a network such as a SAN, and a site including a storage device system similarly connected to high-rank apparatuses via a network are connected to each other via an inter-high-rank-apparatuses network, arbitration-emulation software is installed in each of the high-rank apparatuses. A two-step arbitration is performed, thereby determining one high-rank apparatus. At first, a shared/exclusive control using an already-existing shared volume is performed based on an arbitration conducted within the site. Next, a shared/exclusive control based on an arbitration conducted between the sites is performed by high-rank apparatuses each of which has won the arbitration within each site.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to selectively bypass a portion of the information specified by a user of the software and to provide non-bypassed information to the user and not said bypassed portion.

Abstract: A multi processor system 1 comprises a plurality of processors 21 to 25, a system bus 30 and a main system memory 40. Each processor 21 to 25 is connected to a respective cache memory 41 to 45, with each cache memory 41 to 45 in turn being connected to the system bus 30. The cache memories 41 to 45 store copies of data or instructions that are used frequently by the respective processors 21 to 25, thereby eliminating the need for the processors 21 to 25 to access the main system memory 40 during each read or write operation. Processor 25 is connected to a local memory 50 having a plurality of data blocks (not shown). According to the invention, the local memory 50 has a first port 51 for connection to its respective processor 25. In addition, the local memory 50 has a second port 52 connected to the system bus 30, thereby allowing one or more of the other processors 21 to 24 to access the local memory 50.