Abstract: Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

Abstract: An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.

Abstract: Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).

Abstract: According to one embodiment, a controller of a memory system executes communication with a host in conformity with a standard of NVM express. When fetching a command from a first submission queue, the controlled of the memory system determine the number of commands to be fetched with the number of free slots among a plurality of slots included in a first completion queue as an upper limit. The controller fetches the determined number of commands from the first submission queue.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: The present application discloses a magnetic disk management method, an apparatus and an electronic device by providing an engine layer including a plurality of space files and an encapsulation layer including a file directory tree of a space file structure; where the engine layer responds to a data management operation performed for a target space file of the file directory tree output by the engine layer, and a target magnetic disk space corresponding to the target space files is determined through the address association list of the encapsulation layer, and data management is performed on the data in the target magnetic disk space. Thereby, different data can be isolated by different space files when entering through the engine layer, which ensures that security issues such as leakage of the data in the magnetic disk will not occur.

Abstract: Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

Abstract: Embodiments that process data are described. For instance, a method includes receiving, at a first disk management device in a storage system, an access request for accessing data in a plurality of disks associated with the storage system. The method further includes determining whether a first access engine for accessing the plurality of disks in the first disk management device is available. The method further includes redirecting the access request to a second disk management device in the storage system if it is determined that the first access engine is unavailable, wherein a second access engine in the second disk management device is available to access the plurality of disks. By means of this method, effective data access can be performed when an access engine of a disk management device is unavailable, thus realizing a more stable access capability and improving the user experience.

Abstract: The present disclosure generally relates to improving data transfer in a data storage device. Not only prior to executing a command received from a host device, but even before scheduling the command, the data storage device parses the command and fetches physical region page (PRP) entries and/or scatter-gather list (SGL) entries. The fetching occurs just after receiving the command. Additionally, the host buffer pointers, which are described in PRP or SGL methods, associated with the entries are also fetched prior to scheduling the command. The fetching is a function of device constraints, queue depth, and/or tenant ID in a multi-tenant environment. The immediate fetching of at least part of the host buffers improves device performance, particularly in sequential write or read look ahead (RLA) scenarios.

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: Techniques performed by a computing device of storing data in a data storage system are provided. A method includes (a) storing references to write commands within entries of a first chained hash table (CHT), the first CHT being pointed to by a first data structure representative of a logical disk; (b) keeping track of a load factor of the first CHT during operation; and (c) in response to determining that the load factor of the first CHT has transitioned outside of predetermined bounds: (1) creating a second CHT and a second data structure representative of the logical disk, the second CHT being pointed to by the second data structure; (2) linking the second data structure to the first data structure via a linked list; and (3) storing references to new write commands directed at the logical disk within entries of the second CHT rather than the first CHT.

Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

Abstract: A method for performing verification and testing of a device under test (DUT) is described. The method includes receiving, by a processing device, inputs from a user regarding a hardware design for the DUT. The processing device presents cover group attribute suggestions to the user based on the hardware design and receives cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions. Based on the cover group information, the processing device automatically generates verification code, including one or more cover group definitions.

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.

Abstract: A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

Abstract: A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.