Patents Examined by Hewy H Li
  • Patent number: 11544198
    Abstract: A data storage device may include a first memory apparatus including a plurality of data blocks having data classified in units of data blocks; a second memory apparatus in communication with the first memory apparatus to store data cached from the first memory apparatus; and a controller in communication with the first memory apparatus and the second memory apparatus. The controller is configured to perform a caching group based caching operation by controlling the first memory apparatus to cache data from the first memory apparatus to the second memory apparatus on a caching group basis. Each caching group includes a first data block requested for caching and one or more other data blocks having the same write count as a write count of the first data block.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: So Hyun Kim, Kyung Soo Lee
  • Patent number: 11513727
    Abstract: A method, computer program product, and computer system for extending, by a computing device, transaction log page-buffers for Non-Volatile Random Access Memory (NVRAM) onto a solid state drive (SSD). It may be determined whether a bandwidth limit of the NVRAM has reached a threshold bandwidth. An IO may be processed on one of the NVRAM and the SSD based upon, at least in part, whether the bandwidth limit of the NVRAM has reached the threshold bandwidth.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company, LLC
    Inventors: Vamsi K. Vankamamidi, Ronen Gazit, Philippe Armangau, Amitai Alkalay
  • Patent number: 11467969
    Abstract: An accelerator and a system for accelerating operations are disclosed. A respective apparatus comprises an interface configured to couple the apparatus to an interconnect, a plurality of processing modules, each processing module configured to process data, a control module configured to control processing of each of the plurality of processing modules, and a cache module configured to store at least a portion of data processed by at least one of the plurality of processing modules. Each processing module includes a processing core configured to process data by performing an operation on the data using a plurality of processing elements, an input control unit configured to retrieve data via the interface and data stored in the cache module and to provide the retrieved data to the processing core, and an output control unit configured to provide data processed by the processing core to the interface and the cache module.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 11, 2022
    Assignee: Almotive Kft.
    Inventors: Gyula Nagy, Márton Fehér
  • Patent number: 11461238
    Abstract: A memory controller for controlling a plurality of memory chips of a non-volatile memory includes a first core configured to identify a size of a remaining space of a page to be written in a memory chip on which a write operation is to be performed among the plurality of memory chips and fetch a first write command from a first submission queue among a plurality of submission queues included in a host, the first write command being related to data having a size corresponding to that of the remaining space of the page to be written, and a second core configured to control the non-volatile memory to store data related to the fetched first write command in the remaining space of the page to be written.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Soo Jang
  • Patent number: 11461254
    Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: October 4, 2022
    Assignee: Ambarella International LP
    Inventors: Manish Singh, Dingxin Jin
  • Patent number: 11442668
    Abstract: A service management device includes a memory, and a processor coupled to the memory and configured to acquire respective execution times of programs that implement a service, identify a first volume having a largest influence on a response time of the service based on the respective execution times of the programs, where the first volume being any one of volumes of a storage device, and at least one of the programs writing and reading data to and from the storage device, and set a priority of writing and reading of data to and from the first volume higher than priorities of writing and reading of data to and from a remaining volume of the volumes.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: September 13, 2022
    Assignee: Fujitsu Limited
    Inventor: Shinya Kuwamura
  • Patent number: 11442650
    Abstract: Storage management techniques involve: obtaining a historical usage of storage capacity for a storage device, and a historical feature characterizing the historical usage of storage capacity; generating a predicted usage of storage capacity for the storage device based on the historical feature and a predictor for predicting a usage of storage capacity; and updating the predictor by comparing the historical usage of storage capacity with the predicted usage of storage capacity. Therefore, such techniques can accurately predict the usage of storage capacity for the storage device.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 13, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jie Huang, Xudong Wang, Ming Wang, Xiaoyu Ren
  • Patent number: 11442857
    Abstract: Dynamic caching policies and/or dynamic purging policies are provided for modifying the entry and eviction of content to the cache (e.g., storage and/or memory) of a caching server based on the current and past cache performance and/or demand. The caching server may modify or replace a configured policy when cache performance is below one or more thresholds. Modifying the caching policy may change caching behavior of the caching server by changing the conditions that control the content that is entered into cache or the content that is deferred and not entered into cache after a request. This may include assigning different probabilities for entering the same content into cache based on different caching policies. Modifying the purging policy may change eviction behavior of the caching server by changing the conditions that control the cached content that is selected and removed from cache.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 13, 2022
    Assignee: Edgecast Inc.
    Inventors: Marcel Eric Schechner Flores, Derrick Sawyer
  • Patent number: 11435921
    Abstract: For each of multiple storage volumes of a distributed storage system, it is determined whether the storage volume has a relatively high potential deduplicability or a relatively low potential deduplicability. Responsive to determining that the storage volume has the relatively high potential deduplicability, a first write flow is executed for each of a plurality of write requests directed to the storage volume, the first write flow utilizing content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system. Responsive to determining that the storage volume has the relatively low potential deduplicability, a second write flow is executed for each of a plurality of write requests directed to the storage volume, the second write flow utilizing non-content-based signatures of respective data pages of the storage volume to store the data pages in storage devices of the distributed storage system.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Xiangping Chen
  • Patent number: 11416410
    Abstract: A memory system includes: a memory device suitable for storing map information; and a controller suitable for storing a portion of the map information in a map cache, and accessing the memory device based on the map information stored in the map cache or accessing the memory device based on a physical address that is selectively provided together with an access request from a host, wherein the map cache includes a write map cache suitable for storing map information corresponding to a write command, and a read map cache suitable for storing map information corresponding to a read command, and wherein the controller provides the host with map information that is outputted from the read map cache.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Hye-Mi Kang
  • Patent number: 11409667
    Abstract: A deduplication engine maintains a hash table containing hash values of tracks of data stored on managed drives of a storage system. The deduplication engine keeps track of how frequently the tracks are accessed by the deduplication engine using an exponential moving average for each track. Target tracks which are frequently accessed by the deduplication engine are cached in local memory, so that required byte-by-byte comparisons between the target track and write data may be performed locally rather than requiring the target track to be read from managed drives. The deduplication engine implements a Least Recently Used (LRU) cache data structure in local memory to manage locally cached tracks of data. If a track is to be removed from local memory, a final validation of the target track is implemented on the version stored in managed resources before evicting the track from the LRU cache.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 9, 2022
    Assignee: Dell Products, L.P.
    Inventors: Venkata Ippatapu, Ramesh Doddaiah
  • Patent number: 11398894
    Abstract: A method comprising initializing, by a processor, a field identification (FID) field and a file type field in a memory encryption counter block associated with pages for each file of a plurality of files stored in a persistent memory device (PMD), in response to a command by an operating system (OS). The file type field identifies whether each file associated with FID field is one of an encrypted file and a memory location. The method includes decrypting data of a page stored in the PMD, based on a read command by a requesting core. When decrypting, determining whether the requested page is an encrypted file or memory location. If the requested page is an encrypted file, performing decryption based on a first encryption pad generated based on the file encryption key of the encrypted file and a second encryption pad generated based on a processor key of the secure processor.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 26, 2022
    Assignee: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATION, INC.
    Inventor: Amro Awad
  • Patent number: 11392499
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Patent number: 11379371
    Abstract: A data management system includes a data storage device, a buffer memory, and a controller. The buffer memory is configured to temporally store data read during a reading operation of the data storage device. The controller is configured to, after transmitting a data input/output (I/O) instruction to the data storage device upon an indication of a data reading request, allocate the buffer memory, register a buffer cache of the buffer memory, allocate a direct memory access (DMA) address for the buffer memory, and release the DMA address.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: July 5, 2022
    Assignees: Research & Business Foundation Sungkyunkwan University, High Performance Computing Research Center
    Inventors: Jinkyu Jeong, Gyusun Lee
  • Patent number: 11372764
    Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method also maintains, for the data element, a read access count that is incremented each time a data element is read in the cache. The method removes the data element from the higher performance portion of the cache in accordance with a cache demotion algorithm. If the write access count is below a first threshold and the read access count is above a second threshold, the method places the data element in the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11366761
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of parallel operation elements each including a memory cell. The memory controller is configured to control the plurality of parallel operation elements. In reading data from the non-volatile memory, the memory controller is configured to sequentially instruct the plurality of parallel operation elements to perform a sense operation of sensing data stored in the memory cell included in each of the plurality of parallel operation elements. In a case where an operation period of the sense operation of any one of the plurality of parallel operation elements is expired, the memory controller instructs the one of the plurality of parallel operation elements to perform a transfer operation for the data without checking a status of the one of the plurality of parallel operation elements.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventor: Takashi Kondo
  • Patent number: 11360711
    Abstract: A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chulseung Lee, Seonghoon Woo, Kyuwook Han, Daehyun Kim
  • Patent number: 11354040
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Patent number: 11347404
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, a first amount of storage space reserved by RAID for a RAID rebuild of a failed drive. A second amount of the storage space reserved by a file system may be identified, wherein the storage space may be shared between the RAID and the file system. The RAID rebuild of the failed drive may be performed. The first amount of the storage space may be allocated to the RAID from the second amount of the storage space reserved by the file system.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 31, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Vamsi Vankamamidi, Philippe Armangau, Shuyu Lee
  • Patent number: 11340790
    Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventors: Joo Young Lee, Kyeong Rho Kim, Kyung Hoon Lee