Patents Examined by Hien N Nguyen
  • Patent number: 11738214
    Abstract: An apparatus having an implantable ultrasound generating treating device to induce brain disorder treatment, suitable for implantation in or under the skull bone of a patient, includes several ultrasound generating transducers, which are connectable by a common electrical connection circuit to a generator, and wherein the ultrasound generating transducers each have one or several operating frequencies. The transducers include the group of transducers having several transducers driven by a same electrical drive signal, and connected to the generator system by a common electrical connection circuit, where the electric drive signal serves both as power signal and as a control signal for operating selectively, within said group, at least one or the other of a first transducer or sub-group of transducers, and of a second transducer or sub-group of transducers. The apparatus is also used to treat brain disorders.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 29, 2023
    Assignees: SORBONNE UNIVERSITE, ASSISTANCE PUBLIQUE—HÔPITAUX DE PARIS, CARTHERA
    Inventors: Alexandre Carpentier, Michael Canney, Matthieu Cholvy
  • Patent number: 11735265
    Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a memory cell array including a plurality of selected blocks and a plurality of non-selected blocks; and a row decoder including a block decoder configured to switch between the selected block and the non-selected block. The row decoder switches a block determined to be a defective block to a non-selected block and switches a block determined not to be a defective block to a selected block, on the basis of the multi-level data. The block decoder includes a defective block flag circuit including a plurality of latch circuits configured to store multi-level data.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: August 22, 2023
    Assignee: Kioxia Corporation
    Inventor: Yukio Komatsu
  • Patent number: 11735271
    Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells, and a peripheral circuit configured to perform a read operation and a dummy read operation on the memory block. A discharge slope of a pass voltage applied to the memory block during the read operation is greater than a discharge slope of a dummy pass voltage applied to the memory block during the dummy read operation.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 22, 2023
    Assignee: SK hynix Inc.
    Inventors: Jong Wook Kim, Noh Yong Park
  • Patent number: 11735259
    Abstract: A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Carlos H. Diaz, Hung-Li Chiang, Tzu-Chiang Chen, Yih Wang
  • Patent number: 11727963
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 11724130
    Abstract: A wearable ultrasound device and method of using the device includes a power controller with a power source and at least one integrated circuit that delivers electrical power to an applicator. The applicator is electrically coupled to the power controller and a surface of the applicator transmits ultrasound to a wearer for a given duration. The applicator includes radio frequency (RF) drive electronics, an ultrasound transducer coupled to the drive electronics, a monitoring apparatus that includes a thermal cutoff coupled to the drive electronics, where the monitoring apparatus monitors a temperature of the applicator surface and the thermal cutoff turns off the applicator, if the temperature exceeds a pre-defined threshold, and a coupling bandage coupled to the applicator, where the bandage positions the surface of the applicator proximate to a wearer at a location on the body of a wearer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 15, 2023
    Assignee: ZETROZ SYSTEMS LLC
    Inventors: George K. Lewis, Jr., Bryant Guffey, JoAnne Guarino, Shane Fleshman, Matthew Langer
  • Patent number: 11727975
    Abstract: A nonvolatile memory device of an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction intersecting the first direction; a memory cell disposed between the first layer and the second layer, and has first and second terminals, the memory cell including a variable resistance element; a first drive circuit capable of supplying a first potential and a second potential lower than the first potential; a second drive circuit supplying a third potential having a different polarity from a polarity of the first potential; a third drive circuit capable of supplying the second potential and a fourth potential higher than the second potential; a fourth drive circuit supplying a fifth potential having a different polarity from a polarity of the first potential; and a control circuit electrically connected to the first to fourth drive circuits.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Katsuhiko Hoya
  • Patent number: 11724132
    Abstract: Disclosed are methods of obtaining zero vergence ultrasound waves for providing sonodynamic therapy with ultrasound waves. The method includes coupling a sonodynamic therapy device with an array of flat piezoelectric transducers to a skin surface. A controller is configured to generate an electrical drive signal at a frequency, modulate the drive signal, and drive the transducer with the modulated drive signal at the frequency to produce a zero vergence ultrasound wave to produce an average acoustic intensity sufficient to activate a sonosensitizer in a treatment region without damaging healthy cells in the treatment region.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: August 15, 2023
    Assignee: Alpheus Medical, Inc.
    Inventors: Vijay Agarwal, Braden Eliason, Jeremy Ling
  • Patent number: 11721393
    Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih
  • Patent number: 11723206
    Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: August 8, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11705216
    Abstract: A determination is made by a processing device included in a memory component that an operation to program data to a location in the memory component has failed, the data is programmed to a different location in the memory component by the processing device upon determining the operation has failed, and a notification that the data has been programmed to the different location in the memory component is provided by the processing device to a processing device operatively coupled to the memory component.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Adam J. Hieb
  • Patent number: 11705196
    Abstract: Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: July 18, 2023
    Assignee: TetraMem Inc.
    Inventors: Miao Hu, Ning Ge
  • Patent number: 11705198
    Abstract: A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: July 18, 2023
    Assignee: CYBERSWARM, INC.
    Inventors: Viorel-Georgel Dumitru, Cristina Besleaga Stan, Alin Velea, Aurelian-Catalin Galea
  • Patent number: 11701134
    Abstract: Methods for performing non-invasive thrombolysis with ultrasound using, in some embodiments, one or more ultrasound transducers to focus or place a high intensity ultrasound beam onto a blood clot (thrombus) or other vascular inclusion or occlusion (e.g., clot in the dialysis graft, deep vein thrombosis, superficial vein thrombosis, arterial embolus, bypass graft thrombosis or embolization, pulmonary embolus) which would be ablated (eroded, mechanically fractionated, liquefied, or dissolved) by ultrasound energy. The process can employ one or more mechanisms, such as of cavitational, sonochemical, mechanical fractionation, or thermal processes depending on the acoustic parameters selected. This general process, including the examples of application set forth herein, is henceforth referred to as “Thrombolysis.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: July 18, 2023
    Assignee: The Regents of the University of Michigan
    Inventors: Adam D. Maxwell, Zhen Xu, Hitinder S. Gurm, Charles A. Cain
  • Patent number: 11705181
    Abstract: Methods of operating a memory device are disclosed. A method may include determining an amount of activity associated with at least one memory bank of a memory device. The method may further include adjusting a row hammer refresh rate for the at least one memory bank based on the amount of activity associated with the at least one memory bank. Memory devices and systems are also described.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Joo-Sang Lee
  • Patent number: 11688461
    Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Makoto Hirano, Jinyoung Kim
  • Patent number: 11684425
    Abstract: An X-ray fluoroscopic imaging apparatus which can accurately perform enhancement processing of a device and can also reduce a burden on an operator is provided. An exclusion region E is set so as to surround an obstacle on an X-ray image generated by an image generation unit. A marker extraction unit extracts a marker from a region except for an exclusion region in the X-ray image. An integration unit superimposes a predetermined number of X-ray images on the basis of the position of the marker to generate an integrated image. In this case, detecting obstacle as a marker can be avoided, so the integrated image becomes an image with a stent suitably highlighted. Even in cases where it is difficult to set the region-of-interest so that an obstacle falls out of the range, such as a case in which an obstacle overlaps or is in proximity to a stent, it is easy to set the exclusion region so that the marker is out of range and the obstacle falls within the range.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 27, 2023
    Assignee: Shimadzu Corporation
    Inventor: Shota Sato
  • Patent number: 11682440
    Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
  • Patent number: 11681457
    Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
  • Patent number: 11678897
    Abstract: A surgical method treats infections on a lead positioned at least partially within a patient's body. The surgical method includes uncoupling the lead from a pulse generator. The lead is then coupled to an ultrasound wave generator. Ultrasound waves are propagated from the ultrasound wave generator through the lead. Systems are disclosed.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 20, 2023
    Assignee: MEDTRONIC, INC.
    Inventors: Alan Cheng, Jian Cao, Zhongping Yang