Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

Abstract: A calorie estimation apparatus and method that analyze a user's skin spectrum to determine calories of food and drink that the user has ingested are provided. The calorie estimation apparatus includes a spectrum measurer configured to measure a skin spectrum of a user; and a processor configured to determine a noise of the measured skin spectrum, and estimate calories consumed by the user based on the determined noise.

Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Abstract: A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.

Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

Abstract: An apparatus for treating vascular thrombosis with ultrasound, includes a therapeutic ultrasonic transducer, suitable for generating focused ultrasonic waves that propagate along an emission axis; an imaging ultrasonic transducer associated with the therapeutic transducer; a means for moving the focal spot of the therapeutic ultrasonic transducer along the emission axis with respect to the imaging transducer; a motorized mechanical system for translating the transducers along at least a first axis parallel to the emission axis and a second axis perpendicular to the first; and an electronic control system for driving the motorized mechanical system and the means for moving the focal spot of the therapeutic transducer.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

Abstract: The present disclosure provides an ultrasound therapy system and a dose control method. The system includes: a control device; a first ultrasound irradiation device configured to generate multiple groups of ultrasound irradiation doses driven by the control device and conduct ultrasound irradiation on a cell culture device with multiple groups of abnormally proliferating living cells; a characterization image capture device configured to capture performance characteristic data of living cells in the cell culture device, where the control device is further configured to determine an ultrasound irradiation dose corresponding to at least one group of abnormally proliferating living cells with a cell target characteristic characterization as a target ultrasound irradiation dose according to the performance characteristic data; and a second ultrasound irradiation device configured to conduct ultrasound irradiation of the target ultrasound irradiation dose on a living organism with abnormal proliferation.

Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Abstract: Disclosed herein is a novel technique that employs non-invasive ultrasound for spatiotemporal modulation of the refractive index in a medium to define and control the trajectory of light within the medium itself, thereby creating a virtual sculpted lens. By varying the amplitude of ultrasonic waves in the medium, the numerical aperture (NA) value of the virtual sculpted lens can be changed. The location of the focus of the virtual sculpted lens can be precisely scanned within a scattering tissue.

Abstract: Apparatus and methods for deactivating bronchial nerves extending along the secondary bronchial branches of a mammalian subject to treat asthma and related conditions. An ultrasonic transducer (11) is inserted into the bronchus as, for example, by advancing the distal end of a catheter (10) bearing the transducer into the secondary bronchial section to be treated. The ultrasonic transducer emits circumferential ultrasound so as to heat tissues throughout circular impact volume (13) as, for example, at least about 1 cm3 encompassing the bronchus to a temperature sufficient to inactivate nerve conduction but insufficient to cause rapid ablation or necrosis of the tissues. The treatment can be performed without locating or focusing on individual bronchial nerves. The apparatus and methods utilized for lung tumor ablation.

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

Abstract: A vertical nonvolatile memory device including a memory cell string using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction and having a first surface opposite a second surface, a plurality of gates and a plurality of insulators alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.

Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV?1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.