Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: A semiconductor device includes a memory cell array having a plurality of memory cells respectively coupled to first and second bit lines, page buffers, and a bit line selection circuit including a plurality of selection circuit blocks configured to couple the first or second bit lines to the page buffers. A pair of the first and second bit lines is disposed in each of the plurality of selection circuits so that first bit lines of adjacent selection circuit blocks face each other, or second bit lines of adjacent selection circuit blocks face each other.

Abstract: A semiconductor memory device, a memory system including the same and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array having a plurality of memory cells, peripheral circuits configured to perform a program operation using an incremental step pulse programming (ISPP) method on selected memory cells from among the plurality of memory cells. The semiconductor memory device includes an additional program using set program voltages to set memory cells, and a control logic configured to control the peripheral circuits to perform the program in the manner of the ISPP method and the additional program.

Abstract: A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

Abstract: A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.

Abstract: When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line's voltage is dropped briefly, can be applied to neighboring non-selected word lines.

Abstract: A tissue clip for adjoining tissues including a body portion, a biasing mechanism interconnecting the body portion to a tissue grasping mechanism, the grasping mechanism having a first condition wherein the grasping mechanism is extending against and away from the body portion and a second condition wherein the grasping mechanism is biased against the body portion. A tissue clip and deployer combination. A method of interconnecting tissue by deploying the tissue clip, puncturing tissue to be interconnected with the tissue clip, and interconnecting the tissue. A method of treating an aneurism by deploying the tissue clip at an aneurism site, closing off the aneurism site with the tissue clip, and treating the aneurism. A method of imaging a surgical procedure with ultrasound by modifying a surface of a metal surgical instrument, and imaging the metal surgical instrument with ultrasound during a surgical procedure.

Abstract: Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a current across the memory cell to read a content of the memory cell. During a subsequent read cycle of the memory cell, a subsequent current is applied across the memory cell in the opposite direction to read the content of the memory cell.

Abstract: A network apparatus, wherein a bearer is set between the network apparatus and a gateway apparatus connects a radio access network and a core network, including: a tunneling processing unit that encapsulates user data in accordance with a tunneling protocol; a data combining unit that generates combined data in which a plurality of the encapsulated user data to be transmitted to the same the gateway apparatus are combined; a header generation unit that generates a header of the network protocol storing the bearer identifier of the bearer transmitting user data included in the combined data; and a transmission unit that transmits a packet of the combined data having the header added thereto to the gateway apparatus.

Abstract: MRAM cell including a magnetic tunnel junction including a sense layer, a storage layer, a tunnel barrier layer and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer is arranged such that the sense magnetization can be switched from a first stable direction to another stable direction opposed to the first direction. The switched sense magnetization generates a sense stray field being large enough for switching the storage magnetization according to the switched sense magnetization, when the magnetic tunnel junction is heated at the writing temperature. The disclosure also relates to a method for writing to the MRAM cell with increased reliability and reduced power consumption.

Abstract: Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.

Abstract: In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.

Abstract: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combine (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.

Abstract: Described is an applicator for RF, ultrasound, and light skin treatment. The applicator allows a protrusion of skin to be formed within a cavity and maintained for a desired time, enables good coupling of the treatment energy with the skin and avoids negative pressure adversely affecting the skin.

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.

Abstract: A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.

Abstract: In an acoustic wave detection probe provided with a light guide section that guides measuring light such that the measuring light is outputted toward a subject and an acoustic wave transducer that detects a photoacoustic wave generated in the subject by the projection of the measuring light, the light guide section includes a homogenizer that flat-tops an energy profile of the measuring light entered from the upstream side of the optical system, a light condensing member that condenses the measuring light transmitted through the homogenizer, and a bundle fiber which includes a plurality of optical fibers and is disposed such that the measuring light transmitted through the light condensing member enters from an entrance end of the bundle fiber.

Abstract: A memory device consumes low power, has high capacity, and is shared by a plurality of processors. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors.

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. The low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. In some applications where only the integrated circuit can read the data, a second control signal internal to the integrated circuit generates start, stop, device ID, read pattern, starting address, and actual read cycles, while the first control signal external to the integrated circuit can do the same for the program or erase path.

Abstract: A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.