Patents Examined by Hien Nguyen
  • Semiconductor device
    Patent number: 9496044
    Abstract: A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103) which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (105), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element (102) and the threshold voltage of the second memory element (103) during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element (102) and the voltage of a second bit line (/BL) which is connected to the second memory element (103) during the application of erase pulse.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: November 15, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Tamiyu Kato
  • Method and system of programmable resistive devices with read capability using a low supply voltage
    Patent number: 9496033
    Abstract: A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: November 15, 2016
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • System and method for therapy and diagnosis comprising optical components for distribution of radiation
    Patent number: 9486640
    Abstract: A system and method for interactive therapy and diagnosis of a human or animal comprising at least one first radiation source for emission of a diagnostic radiation, at least one second radiation source for emission of a therapeutic radiation, and at least one radiation conductor adapted to conduct radiation to a tumor site at or in said human or animal. A non-mechanical operation mode selector directs the therapeutic radiation and/or the diagnostic radiation to the tumor site through the radiation conductors. The operation mode selector means is preferably a non-mechanical optical switch and/or an optical combiner. The system may be used for interactive interstitial photodynamic tumor therapy.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: November 8, 2016
    Assignee: SpectraCure AB
    Inventors: Marcelo Soto Thompson, Stefan Andersson Engels, Sune Svanberg
  • Anti-fuse, anti-fuse array and method of operating the same
    Patent number: 9490259
    Abstract: An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yong Sun Jung
  • Semiconductor memory device and operating method thereof
    Patent number: 9478289
    Abstract: A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 25, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yong Hwan Hong, Byung Ryul Kim, Dae Il Choi
  • Memory system and controller
    Patent number: 9478293
    Abstract: A memory system includes a semiconductor memory device and a controller. The semiconductor memory device performs a writing operation with either a first writing method or a second writing method. The controller selects one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device. The controller selects the writing method in accordance with a storage location in the semiconductor memory device targeted by the write instruction.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 25, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsufumi Yanagida, Masanobu Shirakawa, Toshihiro Suzuki
  • Non-volatile memory with adjustable cell bit shape
    Patent number: 9472281
    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 18, 2016
    Assignee: HGST NETHERLANDS B.V.
    Inventors: Luiz M. Franca-Neto, Kurt Allan Rubin
  • Poly ?-amino acid and ferroelectric memory element using same
    Patent number: 9464167
    Abstract: Ferroelectric memory elements which contain a poly ?-amino acid which is a copolymer containing a glutamic acid-?-ester unit represented by the formula (I), defined herein, and a glutamic acid-?-ester unit represented by the formula (II), defined herein, in a molar ratio of units of formula (I) to units of formula (II) of 10/90-90/10 are useful as recording elements such as RFID and the like.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 11, 2016
    Assignee: AJINOMOTO CO., INC.
    Inventors: Satoru Ohashi, Sei Uemura, Manabu Kitazawa, Toshihide Kamata
  • Memory device, method of controlling memory device, and memory system
    Patent number: 9466367
    Abstract: A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: October 11, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenichi Murooka
  • Methods and apparatuses for generating a steerable pressure field in a shock wave lithotripter
    Patent number: 9456835
    Abstract: Lithotripter apparatuses and methods are provided for selectively modifying an acoustic pressure field and can include a shock wave source operable to generate a shock wave having a substantially axisymmetric acoustic pressure field, an acoustic focusing member positioned between the shock wave source and a target, and an acoustic barrier positioned between the shock wave source and the acoustic focusing member. The acoustic barrier can be operable to selectively block a portion of the shock wave generated by the shock wave source such that the substantially axisymmetric pressure field is transformed into a modified acoustic pressure field.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 4, 2016
    Assignee: DUKE UNIVERSITY
    Inventors: Pei Zhong, Walter Neal Simmons, Georgy N. Sankin, Nathan Smith, Franklin Hadley Cocks, Glenn M. Preminger
  • Self-refresh device and semiconductor device including the self-refresh device
    Patent number: 9460774
    Abstract: A self-refresh device is disclosed, which relates to a technology for generating a self-refresh period by reflecting refresh characteristics of an actual cell in a semiconductor device. The self-refresh device includes: a period generation unit configured to output a period control signal by comparing an output voltage of a dummy cell with a reference signal; a phase detection unit configured to detect a phase of the period control signal in response to an oscillation signal having a fixed period; and a refresh signal output unit configured to output a self-refresh period signal in response to the oscillation signal and an output signal of the phase detection unit.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 4, 2016
    Assignee: SK hynix Inc.
    Inventor: Hyeng Ouk Lee
  • Quantizing circuits having improved sensing
    Patent number: 9449664
    Abstract: A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. The quantizing circuit includes a combination circuit configured to combine an analog input signal with an analog feedback signal to produce a delta signal. The quantizing circuit also includes an integrator configured to receive and integrate the delta signal to produce a sigma signal. The quantizing circuit also includes an analog-to-digital converter configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Russel J. Baker
  • Dynamic redundancy repair
    Patent number: 9449720
    Abstract: The disclosed memory device technology for implementing dynamic device repair includes a memory array, a redundancy array and a redundancy mapping store. The memory array includes memory cells and the redundant array includes redundancy cells. The memory device also includes circuitry configured to execute a write operation and a read operation in response to respective commands, using a dynamic redundancy repair method to replace the temporary defective cells in the memory array with the redundancy cells in the redundancy array.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: September 20, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Memory device
    Patent number: 9437274
    Abstract: A memory device may include a plurality of word lines each word line being operably coupled to one or more memory cells; a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines; wherein the first refresh operation is suitable for preserving stored data for a majority of the memory cells of the memory device and the second refresh operation is suitable for preserving stored data of one or more weak memory cells.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Kwi-Dong Kim, Jun-Hyun Chun
  • Apparatus to store data and methods to read memory cells
    Patent number: 9431103
    Abstract: Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a current across the memory cell to read a content of the memory cell. During a subsequent read cycle of the memory cell, a subsequent current is applied across the memory cell in the opposite direction to read the content of the memory cell.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 30, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Siamak Tavallaei
  • Memory macro configuration and method
    Patent number: 9431075
    Abstract: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sergiy Romanovskyy
  • Interface circuit for high speed communication, and semiconductor apparatus and system including the same
    Patent number: 9419633
    Abstract: An interface circuit of a semiconductor apparatus may include a pulse generation unit, a data clock synchronization unit and a system clock synchronization unit. The pulse generation unit may be configured to generate a burst end pulse from a burst end signal according to a data clock signal. The data clock synchronization unit may be configured to enable a data clock synchronization signal based on the burst end pulse and the data clock signal, and disable the data clock synchronization signal according to a burst end detection signal. The system clock synchronization unit may be configured to generate the burst end detection signal by synchronizing the data clock synchronization signal with a system clock signal.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventor: In Sik Yoon
  • Therapeutic apparatus for treating a subject using magnetic nanoparticles
    Patent number: 9417302
    Abstract: A therapeutic apparatus for treating a subject comprising: a first heating means adapted for heating a first region of the subject, a first control means for controlling the power directed into the first region by the first heating means such that the power stays below a threshold value, a particle heating means adapted for heating magnetic nanoparticles within a second region of the subject using a time varying magnetic field, wherein the first region comprises the second region.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: August 16, 2016
    Assignee: Koninklijke Philips N.V.
    Inventor: Michael Harald Kuhn
  • Semiconductor memory device
    Patent number: 9418732
    Abstract: A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Maejima
  • Microendoscopy with corrective optics
    Patent number: 9411149
    Abstract: Micro-optical imaging is facilitated. According to an example embodiment, a micro-optical probe arrangement includes a GRIN-type lens probe to direct light to and from a specimen. Compensation optics tailored to the probe and aberrations introduced by the lens are located in a light path through the lens, and compensate for the introduced aberrations. A light detector detects light from the specimen, as facilitated by the compensation optics, and generates data characterizing an image of the specimen.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: August 9, 2016
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Benjamin A. Flusberg, Mark Jacob Schnitzer, Tony H. Ko