Abstract: An ultrasound device for therapeutic and aesthetic treatment is disclosed. Different types of hand probes used with the device produce different effects within biological tissues. The device can operate at low frequencies of around 20 KHz to 100 KHz. The device can be operated in continuous mode or pulsed mode with different duty cycles. Software and hardware is used to control power output of the hand probes; treatment time; to perform diagnostics of the hand probes; and to shut off ultrasound emissions in the case of abnormal or incorrect functioning of the hand probes.

Abstract: A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory cell at an intersection of the word line and the semiconductor pillar and having a gate electrically connected to the word line, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a controller that controls a write operation on the memory cell, the write operation including a program operation followed by a verify operation. During the verify operation on the memory cell, the semiconductor pillar is charged after performing a read operation on the memory cell.

Abstract: A memory circuit includes a pre-charging unit configured to charge a metal bit line during a pre-charging period, a sensing unit configured to sense a status of a memory cell coupled to the metal bit line during the pre-charging period, and a sink circuit configured to provide a sink current during the pre-charging period based on the status of the memory cell sensed by the sensing unit.

Abstract: In an acoustic wave detection probe provided with a light guide section that guides measuring light such that the measuring light is outputted toward a subject and an acoustic wave transducer that detects a photoacoustic wave generated in the subject by the projection of the measuring light, the light guide section includes a homogenizer that flat-tops an energy profile of the measuring light entered from the upstream side of the optical system, a light condensing member that condenses the measuring light transmitted through the homogenizer, and a bundle fiber which includes a plurality of optical fibers and is disposed such that the measuring light transmitted through the light condensing member enters from an entrance end of the bundle fiber.

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Abstract: A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined.

Abstract: A semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal.

Abstract: In a device for introducing shock waves into a living body by way of at least one element (4; 12; 14) which transmits the shock waves and upon which shock pulses act, wherein at least one spring member (2) is used for generating the shock waves, a tensioning device is associated with the spring member and allows for an abrupt release of the spring member while delivering a shock pulse.

Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Abstract: A data alignment device includes a buffer configured to buffer a data strobe signal, output a data strobe pulse signal, and buffer inputted data, a latch configured to latch the data in correspondence to the data strobe pulse signal, a first delay configured to delay the data strobe pulse signal and output a delayed signal, a divider configured to divide the delayed signal at a time of activation of a division control signal and generate a plurality of divided signals, a control circuit configured to receive a command signal, a clock, the data strobe signal, and the plurality of divided signals, and control the division control signal for controlling an enable state of the divider, and an alignment circuit configured to align output data in correspondence to the plurality of divided signals.

Abstract: A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process.

Abstract: A forming method includes: applying a first pulse voltage to a second electrode to a variable-resistance nonvolatile memory element in first state; and executing at least once a sequence that includes determining whether the variable-resistance nonvolatile memory element is in a second state, and continuously applying a second pulse voltage followed by a third pulse voltage to the variable-resistance nonvolatile memory element when the variable-resistance nonvolatile memory element is determined not to be in the second state.

Abstract: The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface.

Abstract: A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.

Abstract: The present disclosure relates to methods, devices, and systems for measuring a blood analyte, such as glucose. The disclosure relates more specifically to the use in such methods, devices, and systems of one or more accelerometers to aid in the collection of data, operation of the device, filtering, and other uses. In some embodiments, the accelerometers are three-dimensional accelerometers. An accelerometer can be used in conjunction with analyte monitoring that may be performed with infrared, near infrared, or other wavelength spectroscopy. The accelerometer may allow a monitoring instrument to expect noisy measurement data, indicate positioning of a measurement site for improved expected results, indicate position of the instrument, or help the user properly place or control the instrument.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: A memory device includes a plurality of first interconnects extending in a first direction; a plurality of second interconnects extending in the first direction; a plurality of third interconnects extending in a third direction; and memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects, which surfaces are opposite to each other in the second direction. The resistance change layers are connected to the different second interconnects. A plurality of selectors connect the third interconnects to the first interconnects. One of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect. Gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.

Abstract: The present invention relates to a device, system and a method for extracorporeal Shockwave treatment and in particular, to such a device, system and method in which a Shockwave is produced by a high pressure ballistic device utilizing a regulated high pressure energy source for generating an initial ballistic collision producing an initial Shockwave and an electromagnetic solenoid as reloading apparatus facilitating the formation of subsequent and/or successive Shockwaves.