Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory is configured to execute a first to third read operations. In the first read operation, a first voltage is applied to a selected word line. In the second read operation, a second voltage different from the first voltage and a third voltage are applied to the selected word line. In the third read operation, a fourth voltage different from the first to third voltages and a fifth voltage are applied to the selected word line. An absolute value of a difference between the second voltage and the fourth voltage is different from an absolute value of a difference between the third voltage and the fifth voltage.

Abstract: According to one embodiment, a memory arrangement is described a memory including a memory cell and a sense amplifier coupled to the memory cell having a node whose potential depends on the difference between a current through the memory cell and a reference current, a detection circuit configured to generate a signal representing whether the current through the memory cell is above or below the reference current based on the potential of the node and a limitation circuit configured to receive the signal and to limit the change of the potential of the node caused by the difference between the current through the memory cell and the reference current in response to the signal.

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

Abstract: A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. The quantizing circuit includes a combination circuit configured to combine an analog input signal with an analog feedback signal to produce a delta signal. The quantizing circuit also includes an integrator configured to receive and integrate the delta signal to produce a sigma signal. The quantizing circuit also includes an analog-to-digital converter configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal.

Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.

Abstract: Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Abstract: A virtual rigid body optical tracking system includes a virtual rigid body generator for projecting a virtual rigid body, wherein the virtual rigid body forms a pattern of light on a surface. The virtual rigid body optical tracking system includes an optical detection system for detecting the pattern of light, and a data processing system in communication with the optical detection system. The data processing system is configured to determine a position of the virtual rigid body generator based on the detected pattern of light.

Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference.

Abstract: A CMUT transducer cell suitable for use in an ultrasonic CMUT transducer array has a membrane with a first electrode, a substrate with a second electrode, and a cavity between the membrane and the substrate. The CMUT is operated in a precollapsed state by biasing the membrane to a collapsed condition with the floor of the cavity, and a lens is cast over the collapsed membrane. When the lens material has polymerized or is of a sufficient stiffness, the bias voltage is removed and the lens material retains the membrane in the collapsed state.

Abstract: A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed.

Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

Abstract: A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.

Abstract: A radiation therapy system (1) includes an ultrasound (US) imaging unit (2), a registration unit (30), an US motion unit (44), and a real-time dose computation engine (46). The ultrasound (US) imaging unit (2) generates a baseline and real-time US images (3) of a subject body (4) region including a target and one or more Organs At Risk (OARs). The registration unit (30) deformably registers a planning image (32) and the baseline US image (36), and maps (66) radiation absorptive properties of tissue in the planning image (32) to the baseline US image (36). The US motion unit (44) measures motion of the target volume and OARs during radiation therapy treatment based on the real-time US images. The real-time dose computation engine (46) computes a real-time radiation dose delivered to the tissues based on the tissue radiation absorptive properties mapped from the baseline or planning images to the real-time 3D US images (3).

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio

Abstract: An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and a memory subsystem, coupled to the high speed local memory, including: a module memory controller configured to access the operational data for the processor and the high speed local memory, a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a delay code determining unit configured to output a final delay trim code reflecting process, voltage and temperature (PVT) conditions of the semiconductor memory device, using an internal clock generated for a reference time and a delay circuit configured to reflect a delay of a data line on a clock signal in response to the final delay trim code.