Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

Abstract: A sensor includes a sensor pad configured to be disposed on a portion of a patient's body. A light sheet is disposed on the sensor pad and has a first substrate and a second substrate spaced from one another. The light sheet further includes a light source configured to emit near-infrared light and a light detector configured to detect near-infrared light. The light source and the light detector are disposed between the substrates. The sensor pad is configured to allow light generated by the light source to travel through the portion of the patient's body to the light detector. The light received by the light detector is indicative of oxygen saturation of the portion of the patient's body through which the light travelled.

Abstract: An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Abstract: A memory device includes a static random-access memory (“SRAM”) circuit and a first nonvolatile memory (“NVM”) string, a second NVM string, a first and a second drain select gates (“DSGs”). The SRAM circuit is able to temporarily store information in response to bit line (“BL”) information which is coupled to at the input terminal of the SRAM circuit. The first NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The first DSG is operable to control the timing for storing information at the output terminal of the SRAM to the first nonvolatile memory. The second NVM string having at least one nonvolatile memory cell is coupled to the output terminal of the SRAM. The second DSG controls the timing for storing information at the output terminal of the SRAM to the second nonvolatile memory string.

Abstract: A method for operating a memory device includes performing a single read operation that includes additional one or more combinations of read and/or write cycles, and performing a single write operation that includes additional one or more combinations of read and/or write cycles. For example, a method for auto-correcting errors in a memory device having plurality of memory cells includes performing a first read operation of the memory cell to obtain a first read data value, performing a first write operation to the memory cell to write a second data value, which is a complement of the first data value, into the memory cell, performing a second read operation of the memory cell to obtain a third data value, and performing a second write operation to the memory cell to write a fourth data value, which is a complement of the third data value, to the memory cell.

Abstract: An apparatus for the treatment of skin tissue includes at least one ultrasound transducer for placement on the skin tissue surface; at least two drivers for driving the at least one transducer; a controller which is configured to control the at least two drivers; the controller is configured to drive the at least two drivers at different frequencies to affect different depths in the skin tissue.

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.

Abstract: A method and apparatus for non-invasively determining a concentration of glucose in a subject using optical excitation and detection is provided. The method includes emitting an exciter beam (B1) to irradiate a portion (130) of tissue of the subject, causing physical and chemical changes in the surface, and causing an initial back scattering (D1) of light. The method further includes periodically emitting a probe beam (B2) which irradiates the portion of tissue and causes periodic back scatterings (D2) of light. The initial and periodic back scatterings are detected and converted into electrical signals of at least the amplitude, frequency or decay time of the physical and chemical changes, the back scatterings being modulated by the physical and chemical changes. By differentiating over time at least one of the amplitude, frequency or decay time of the physical and chemical changes, the concentration of glucose may be determined.

Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.

Abstract: A method for ultrasonic imaging comprises: emitting Doppler pulses to a target to be detected; performing a Doppler scan with Doppler pulses; receiving echo signals from the target, wherein the echo signals include Doppler pulse echo signals; processing the echo signals, wherein processing comprises an imaging step, the imaging step comprising parallel processing steps including a 2D image processing step, a flow image processing step, and a spectrum image processing step, wherein the 2D image processing step is configured for processing the echo signals to obtain 2D image signals, the flow image processing step is configured for processing the echo signals to obtain flow image signals, and the spectrum image processing step is configured for processing the echo signals to obtain spectrum image signals; and displaying the processed echo signals.

Abstract: A semiconductor memory device includes a memory cell array having first wires, a second wire, and memory cells connected to the first and second wires, and a control circuit that can apply writing voltages to the second wire. One of the memory cells connected to the selected second wire and a selected first wire is a selected memory cell. One of the memory cells connected to the selected second wire and an unselected first wire is a semi-selected memory cell. When writing data into the selected memory cell, the control circuit selects one from the writing voltages and applies the one writing voltage to a third wire connected to the selected second wire. The control circuit selects the one writing voltage, based on a first current flowing through the second wire when each of the memory cells connected to the selected second wire are set as semi-selected memory cells.

Abstract: An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

Abstract: The invention relates to systems and methods for tomographic imaging of a subject comprising diffuse media by converting measurements of electromagnetic radiation, e.g., fluorescent light, obtained in free space exterior to the subject into data that would be measured if the subject were surrounded by an infinite and homogeneous diffusive medium, e.g., a medium with optical properties equal to the average optical properties of the subject. After applying a transformation to convert measurements to virtually-matched values, propagation of light is simulated from the index-matched surface to a set of virtual detectors exterior to the subject and arranged in a geometrically advantageous fashion, for example, in a planar array, thereby facilitating the use of fast reconstruction techniques.

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

Abstract: A mechanical converter assembly includes an input, a lever stack (multiple levers), and an output. The input is configured to receive a mechanical drive force (or mechanical input signal) from a driver resource. The lever stack translates the received drive force into a mechanical output force (or mechanical output signal). The output of the mechanical converter assembly is configured to apply the mechanical output force produced by the lever stack to a driven element. In one embodiment, use of the lever stack in the mechanical converter assembly provides translational gain in which an amount of translational movement at the input of the mechanical converter assembly results in a substantially greater amount of corresponding translational movement at the output.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract: A device is for thermal treatment of tissue. The device includes (a) an elongated member extending from a proximal end to a distal end insertable to a target position within a body; (b) a housing coupled to the distal end of the elongated member sized and shaped for insertion to a target organ within a living body, the housing including an opening permitting fluid surrounding the housing to enter the housing, the housing further including first and second deflecting elements shaped to diffuse pulses of fluid directed thereagainst; and © a piezoelectric element mounted within the housing between the first and second deflecting elements. The piezoelectric element is oriented to generate pulses in liquid received within the housing toward the first and second deflecting elements.

Abstract: In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal.

Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

Abstract: An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write voltage across a selected one of the resistive memory cells in a first or second direction; first switching units, each of which is disposed between the access circuit and a first end of a corresponding one of the resistive memory cells and turned on in response to a first voltage having a level higher than a predetermined level when the corresponding resistive memory cell is selected during the write operation; and second switching units, each of which is disposed between the access circuit and a second end of the corresponding resistive memory cell and turned on in response to a second voltage having a level equal to or lower than the predetermined level when the corresponding resistive memory cell is selected during the write operation.