Patents Examined by Hieu P Nguyen
  • Patent number: 11031914
    Abstract: A diode linearizer according to the present invention has parallelly mounting linearizer core units on a RF signal path via capacitors between the RF signal path and a ground, thus does not need a switch using an FET, for example, at a time of selectively operating a plurality of linearizer core units. Moreover, the diode linearizer does not need a capacitor in series for blocking a direct current between RF signal input and output terminals. Thus, a range of a gain which can be compensated by the diode linearizer can be increased. Furthermore, an insertion loss of the RF signal path in a state where the diode linearizer is off can be reduced, and a range of a gain expansion in operation can be increased. The switch is not used, or the number of elements of the capacitors which are needed is small, thus a circuit size is also small.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ko Kanaya, Kazuya Yamamoto
  • Patent number: 11031910
    Abstract: A power amplifier module includes a power amplifier circuit and a control IC. The power amplifier circuit includes a bipolar transistor that amplifies power of an RF signal and outputs an amplified signal. The control IC includes an FET, which serves as a bias circuit that supplies a bias signal to the bipolar transistor. The FET is operable at a threshold voltage lower than that of the bipolar transistor, thereby making it possible to decrease the operating voltage of the power amplifier module.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 8, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shota Ishihara, Yasuhisa Yamamoto
  • Patent number: 11031909
    Abstract: A group delay optimization circuit is provided. The group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). Notably, the first signal and the second signal may experience different group delays that can cause the first signal and the second signal to misalign at an amplifier circuit configured to amplify a radio frequency (RF) signal. The group delay optimization circuit is configured to determine a statistical indicator indicative of a group delay offset between the first signal and the second signal. Accordingly, the group delay optimization circuit may minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it may be possible to pre-compensate for the group delay offset in the RF signal, thus helping to improve efficiency and linearity of the amplifier circuit.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 8, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11025209
    Abstract: A power amplifier layout can include multiple cascoded devices each having a radio-frequency transistor coupled to a cascode transistor. An orientation of a radio-frequency transistor of a first cascoded device relative to a cascode transistor of the first cascoded device can be configured to be different than an orientation of a radio-frequency transistor of a second cascoded device relative to a cascode transistor of the second cascoded device.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11025206
    Abstract: Provided is a power supply for envelope tracking, comprising: a first driving unit for finally providing a first current based on a preset and variably-set first high-frequency threshold or threshold interval; a second driving unit for finally providing a second current based on a preset and variably-set second low-frequency threshold or threshold interval; a third driving unit for providing a third current based on a delayed signal; and a superimposing unit for superimposing the first current, the second current, and the third current to provide a supply voltage of a radio-frequency power amplifier. A new power supply for envelope tracking is provided, which is capable of more efficiently providing a supply voltage of the radio frequency power amplifier by superimposing a first current to a third current.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 1, 2021
    Inventors: Qin Xia, Shihong Yang
  • Patent number: 11025205
    Abstract: When a potential difference V1 between a source terminal of an E-type FET (11) and a source terminal of a D-type FET (12) is larger than a threshold voltage Vth, a protection circuit (13) starts an operation to reduce the potential difference V1 such that the potential difference V1 is smaller than the threshold voltage Vth. This makes it possible to prevent destruction of the E-type FET (11) even when a signal to be amplified is an RF signal.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 1, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Eigo Kuwata, Yutaro Yamaguchi
  • Patent number: 11025216
    Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 1, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Sudheer Prasad
  • Patent number: 11018638
    Abstract: A multimode envelope tracking (ET) circuit and related apparatus is provided. The multimode ET circuit is configured to provide an ET voltage(s) to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s) that may correspond to a wider range of modulation bandwidth. In this regard, the multimode ET circuit is configured to switch dynamically and opportunistically between different operation modes based on the modulation bandwidth of the RF signal(s). In examples discussed herein, the multimode ET circuit is configured to support a single amplifier circuit in a high-modulation-bandwidth mode and an additional amplifier circuit(s) in a mid-modulation-bandwidth mode and a low-modulation-bandwidth mode.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 25, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay
  • Patent number: 11011813
    Abstract: A power amplifier module includes a first phase shifter, a second phase shifter, and an electromagnetic shield. The first phase shifter includes a first transmission line assembly to shift a first amplified signal by a first phase angle. The second phase shifter includes a second transmission line assembly to shift a second amplified signal by a second phase angle. The electromagnetic shield is arranged to shield the first transmission line assembly from the second transmission line assembly. The power amplifier module may have, for example, Doherty amplifier configuration.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 18, 2021
    Assignee: NXP B.V.
    Inventor: Ning Zhu
  • Patent number: 11012036
    Abstract: A current reuse type FET amplifier according to the present invention has a capacitance provided between a drain of a first FET in a first stage and a gate of a second FET in a next stage, electrically separates a gate voltage of the second FET from a drain voltage of the first FET, and includes a control circuit controlling the gate voltage of the first FET and the gate voltage of the second FET so that a variation of a drain current of the second FET and a variation of a drain voltage of the first FET are reduced in accordance with a variation of a saturation current Idss of the FET. Furthermore, the current reuse type FET amplifier according to the present invention uses only a depression mode FET to provide a circuit configuration operable with a positive single power source.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 18, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Kurusu
  • Patent number: 11012035
    Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include one or more transient termination circuits coupled to transistor inputs. For example, the transient termination circuits can be configured to reduce the transient response for some signal energy at frequencies below a baseband frequency (fB) of signals being amplified while not similarly reducing the transient response for signal energy near a fundamental frequency (f0) of the signals being amplified.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 18, 2021
    Assignee: NXP USA, Inc.
    Inventors: Arturo Roiz, Justin Nelson Annes, Ricardo Uscola, Terry L. Thomas
  • Patent number: 11005426
    Abstract: A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Min Kim, Jong-Soo Lee, Jong-Woo Lee, Joong-Ho Lee, Ji-Young Lee, Pil-Sung Jang, Thomas Byunghak Cho, Tae-Hwan Jin
  • Patent number: 11005438
    Abstract: An apparatus includes a Transimpedance Amplifier (TIA), an input interface and input masking circuitry. The TIA is configured to convert input current pulses into output voltage pulses. The input interface is configured to receive a control signal indicative of one or more time intervals. The input masking circuitry is configured to prevent the input current pulses from saturating the TIA during the one or more time intervals indicated by the control signal.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: May 11, 2021
    Assignee: APPLE INC.
    Inventor: Ido Luft
  • Patent number: 11005432
    Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: May 11, 2021
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
  • Patent number: 10998859
    Abstract: A dual-input envelope tracking (ET) integrated circuit (ETIC) and related apparatus are provided. The dual-input ETIC includes an ET voltage circuit configured to generate an ET voltage based on an ET voltage and a first set of parameters. The ET voltage may be provided to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s) in an ET power range. The dual-input ETIC also includes a target voltage processing circuit configured to generate the ET target voltage based on a second set of parameters. The dual-input ETIC further includes a control circuit configured to determine the first set of parameters and the second set parameters based at least on the ET power range of the power amplifier circuit(s). As such, it may be possible to optimize the dual-input ETIC performance in a wide-range of modulation bandwidth, thus helping to improve linearity and efficiency of the power amplifier circuit(s).
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 4, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10992277
    Abstract: Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 27, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Li Sun, Dong Ren, Hao Liu, Sudheer Chowdary Gali
  • Patent number: 10985703
    Abstract: Fast envelope tracking systems are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator and a differential error amplifier configured to operate in combination with one another to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The envelope tracking system further includes a differential envelope amplifier configured to amplify a differential envelope signal to generate a single-ended envelope signal that changes in relation to the envelope of the RF signal. Additionally, the differential error amplifier generates an output current operable to adjust a voltage level of the power amplifier supply voltage based on comparing the single-ended envelope signal to a reference signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Serge Francois Drogi, Sabah Khesbak, Hardik Bhupendra Modi
  • Patent number: 10985705
    Abstract: The present disclosure relates to pre-distortion processing methods and apparatus. One example apparatus includes a first pre-distortion part and a second pre-distortion part. The first pre-distortion part includes N digital pre-distortion (DPD) processors. The first pre-distortion part and the second pre-distortion part perform pre-distortion processing on a signal to support a power amplifier in performing linear amplification on the signal.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Vorobyev Andrey, Yiwei Hong, Ting Li
  • Patent number: 10979000
    Abstract: A differential amplifier circuit includes a differential pair including a first field-effect transistor (FET) and a second FET, a first current source that generates a current which flows in the first FET and the second FET, and an output circuit that outputs an output voltage corresponding to a difference between a gate voltage of the first FET and a gate voltage of the second FET in accordance with an operation of the differential pair. A back gate of the first FET is connected to a gate of the first FET, and a back gate of the second FET is connected to a gate of the second FET. A first feedback voltage corresponding to the output voltage is input to the gate of the second FET.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 13, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yusuke Shimamune
  • Patent number: 10978997
    Abstract: An envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The ETIC includes a number of ET circuits configured to generate a number of ET voltages based on a number of ET target voltages, respectively. In examples discussed herein, a selected ET circuit among the ET circuits is configured to generate a respective ET voltage based on a maximum ET target voltage among the ET target voltages. In this regard, the respective ET voltage generated by the selected ET circuit can be used as a reference ET voltage for the rest of the ET circuits in the ETIC. As a result, it may be possible to opportunistically turn off or reduce functionality of one or more other ET circuits in the ETIC, thus helping to reduce peak battery current and improve heat dissipation in an ET amplifier apparatus incorporating the ETIC.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat