Patents Examined by Hieu P Nguyen
  • Patent number: 12034418
    Abstract: A differential amplifier circuit of the present invention includes a differential input circuit including first and second transistors, and amplifies a difference voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor. The differential input circuit a P-channel depletion type transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and the P-channel depletion type transistor operates as a bias current source of the differential amplifier circuit.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 9, 2024
    Assignee: NISSHINBO MICRO DEVICES INC.
    Inventor: Tomoaki Matsuda
  • Patent number: 12034420
    Abstract: A switching amplifier includes a first portion of a power stage; a second portion of a power stage; a pulse-width modulation (PWM) control loop coupled to control inputs of the first portion of the power stage; and a linear amplifier coupled to control inputs of the second portion of the power stage. The PWM control loop controls a first switch and a second switch of the first portion of the power stage. Between current terminals of the first switch and the second switch is a first signal output of the switching amplifier. The linear amplifier controls a third switch and a fourth switch of the second portion of the power stage. Between current terminals of the third switch and the fourth switch is a second signal output of the switching amplifier.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yinglai Xia, Yogesh Kumar Ramadass
  • Patent number: 12028030
    Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: July 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Dongyang Tang, Xinwang Zhang, ChienChung Yang, Earl Schreyer, Sherif Galal
  • Patent number: 12028036
    Abstract: The present invention discloses an amplifier. The bias amplifier includes a signal input end, for inputting an input signal; a voltage input end, for inputting a source voltage; an amplifying circuit, for generating an amplified input signal according to the input signal, and the amplified input signal comprises a fundamental signal, a first harmonic signal and a second harmonic signal, wherein the first harmonic signal is a second order harmonic of the fundamental signal, and the second harmonic signal is a third order harmonic of the fundamental signal; a harmonic filter, coupled between the voltage input end and the amplifying circuit, for filtering the first harmonic signal and the second harmonic signal; and a signal output end, coupled to the harmonic filter, for outputting an output signal according to the amplified input signal.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 2, 2024
    Assignee: RichWave Technology Corp.
    Inventor: Yi-Fong Wang
  • Patent number: 12021489
    Abstract: The present disclosure relates to the field of amplifier circuits (driver amplifiers) for electro-optical modulators, in particular for amplifying an electrical signal for driving electro-optical modulators, an amplifier circuit is proposed for amplifying a signal comprising a gain amplifier, a distributed amplifier, a resistor, and a current source, wherein the input of the distributed amplifier is electrically connected to the output of the gain amplifier; the resistor terminates the input of the distributed amplifier; and the current source is electrically connected in parallel to the resistor. A method of setting a bias voltage of such an amplifier circuit is also proposed. Furthermore, a transmitter, in particular an optical transmitter, comprising such an amplifier circuit and a system comprising such a transmitter and a signal source are also proposed.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: June 25, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Luca Piazzon
  • Patent number: 12015385
    Abstract: Audio amplifier circuit includes a pulse width modulation circuit, an auxiliary loop circuit corresponding to a first variable resistance value and a first variable current value, and a main loop circuit corresponding to a second variable resistance value and a second variable current value. Main loop circuit is coupled between a second node, an output terminal, and a first node. Under a condition that auxiliary loop circuit and main loop circuit are turned on, second variable resistance value is decreased and second variable current value is increased after auxiliary loop circuit enters into a first control state, such that main loop circuit enters into a second control state. First variable resistance value is increased and first variable current value is decreased after main loop circuit enters into second control state, such that auxiliary loop circuit is out of first control state.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 18, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventor: Tzu-Chieh Wei
  • Patent number: 12015382
    Abstract: An apparatus and method for a linearized RF and microwave amplifier current source by feedback of a sampled RF amplifier output signal into a current mirror amplifier bias, to modulate the amplifier bias and produce an increase in a linearized amplifier output. The linearized RF and microwave amplifier is operable over a large bandwidth extending over multiple microwave frequency octaves.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 18, 2024
    Assignee: Scientific Components Corporation
    Inventors: Fuad Haji Mokhtar, Norizwani Mohd Nazari
  • Patent number: 11996807
    Abstract: A new trans-impedance amplifier (TIA) with low noise is provided. The TIA may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, and a pair of capacitors electrically connected in series, which are electrically connected in parallel. The structure can lead to a reduced noise level of the TIA.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 28, 2024
    Assignee: Beken Corporation
    Inventors: Haiyan Zhou, Ronghui Kong, Jiazhou Liu
  • Patent number: 11984856
    Abstract: A low noise amplifier includes: an amplification unit including a first transistor and a second transistor connected in a cascode structure and configured to amplify a signal input to a control terminal of the first transistor; and a gain controller connected between a contact point at which the first transistor and the second transistor are connected to each other and a power source voltage, and configured to adjust a gain of the amplification unit.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 14, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Gyu-Suck Kim, Youngsik Hur
  • Patent number: 11979115
    Abstract: An amplifier system may include a first feedback loop coupled between an output of an amplifier to an input of a modulator for regulating an output voltage driven at the output of the amplifier to a first terminal of a load of the amplifier system, a sense resistor for sensing a physical quantity associated with the amplifier, a second control loop coupled to the sense resistor such that the sense resistor is outside of the second control loop, the second control loop configured to regulate a common-mode voltage at a second terminal of the load, and a common-mode feedforward circuit coupled to the sense resistor and configured to minimize effects of a signal-dependent common-mode feedback of the sense resistor.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Siddharth Maru, Chandra B. Prakash, Tejasvi Das
  • Patent number: 11973478
    Abstract: Apparatuses include (among other components) a first gain device connected to receive an initial voltage, a second gain device in series with the first gain device and connected to receive output of the first gain device, differential gain devices connected to receive outputs from the first gain device and the second gain device (the differential gain devices provide opposite voltage outputs from the apparatus) and high-frequency compensation feed-forward paths connected to the first gain device and the second gain device.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Xu Zhang, Mingming Zhang, Hanqing Zhao, Lukun Zhai, Dan Liu, Xuan Li
  • Patent number: 11973470
    Abstract: Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: April 30, 2024
    Assignee: PSEMI CORPORATION
    Inventor: Tero Tapio Ranta
  • Patent number: 11967750
    Abstract: A low-cost, small-size Wilkinson-type combiner that suppresses the risk of damaging an isolation resistor due to combination loss is provided. The combiner comprises first and second input terminals to which RF signals are input; an output terminal; a wiring line that combines the RF signals input to the first and second input terminals, and outputs the combined signal to the output terminal; an isolation unit provided between the first and second input terminals and formed by a first isolation resistor, a transformer, and a second isolation resistor connected in series; a detection circuit connected to a secondary coil of the transformer and configured to detect a current flowing in the secondary coil; and a determination circuit that outputs a control signal to block input of RF signals to the first and second input terminals if the current flowing in the isolation unit and detected by the detection circuit is higher than or equal to a prescribed value.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 23, 2024
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Sunao Egashira, Kenji Nasu, Yuichiro Suenaga, Naoya Fujimoto
  • Patent number: 11955947
    Abstract: A balun configured for a power range between 500 W and 5 kW output includes a balanced signal port comprising a first connection and a second connection and further includes a single-ended signal port comprising a third connection and a fourth connection, the fourth connection being connected to ground. In addition, the balun includes a first capacitor disposed between the first connection and a first end of a first resistor and a second capacitor disposed between the second connection and the first end of the first resistor. A second end of the first resistor is connected to ground.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: April 9, 2024
    Assignee: TRUMPF HUETTINGER SP. Z O. O.
    Inventors: Andrzej Klimczak, Marcin Golan, Pawel Ozimek
  • Patent number: 11949388
    Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Gen-Sheng Ran, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11949387
    Abstract: A bandpass parametric amplifier circuit includes a plurality of unit cells. At least one unit cell includes a first inductor having a first node coupled to a center conductor and a second node coupled to ground. There is a first capacitor having a first node coupled to the center conductor and a second node coupled to ground. There is a second inductor having a first node coupled to the center conductor. A second capacitor has a first node coupled to a second node of the second inductor. The second capacitor and the second inductor are in series with the center conductor.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 11942898
    Abstract: Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: March 26, 2024
    Assignee: Massachusetts Institute of Technology
    Inventors: Alexander Sergeev Jurkov, David J. Perreault
  • Patent number: 11942866
    Abstract: An error amplifier includes an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter. A first transconductance amplifier adjusts an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also adjusts the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 26, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rajesh Karri, Arun Khamesra
  • Patent number: 11942901
    Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Joseph A Cuggino, Anthony Francis Quaglietta
  • Patent number: 11936354
    Abstract: An amplifier circuit is provided. The amplifier circuit outputs a pair of differential output signals through a first output terminal and a second output terminal. The amplifier circuit includes a first amplifier stage electrically connected to a first node and a second node for amplifying a pair of differential input signals; a second amplifier stage which is electrically connected to the first node and the second node and coupled to the first output terminal and the second output terminal; a first switch, coupled between the first output terminal and a first reference voltage; a second switch, coupled between the second output terminal and the first reference voltage; a third switch, coupled between the first node and the first reference voltage; a fourth switch coupled between the second node and the first reference voltage; and a fifth switch coupled between a second reference voltage and the first amplifier stage.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 19, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang