Abstract: According to an embodiment, there is provided an amplifier circuit including a first capacitive element, a first GM amplifier, and a second GM amplifier. The first GM amplifier includes a first input node, a second input node, and an output node. The output node is connected to one end of the first capacitive element. The second GM amplifier includes a first input node, a second input node, and an output node. The output node is connected to one end of the first capacitive element and the second input node.

Abstract: An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA.

Abstract: A circuit for inductive peaking may include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter and a switch. For example, a first node of the resistor may be connected to the output node of the driver and a second node of the resistor may be connected to the input node of the inverter. The switch may be connected between an output node of the inverter and the first node of the resistor. An input node of the driver may correspond to an input node of the circuit and the output node of the driver may correspond to an output node of the circuit.

Abstract: Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A high-order converter generates a first high-order voltage VU_P and a second high-order voltage VU_N that monotonously change with mutually opposite polarities with respect to high-order m bits (1?m<n) of the digital signal. A low-order converter generates a first low-order voltage and a second low-order voltage that monotonously change with mutually opposite polarities with respect to low-order (n?m) bits of the digital signal. A first amplifier receives one of the first and the second high-order voltages and one of the first and the second low-order voltages to output one differential analog signal. Having a configuration in common with the first amplifier, a second amplifier receives another of the first and the second high-order voltages and another of the first and the second low-order voltages to output another differential analog signal.

Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

Abstract: The invention relates to a high-performance audio amplifier intended to control at least one loudspeaker, the amplifier comprising a pre-amplification stage that receives an input signal, a power amplification stage connected to the pre-amplification stage and a feedback that delivers to the pre-amplification stage an image of the output signal, the power amplification stage comprising two power supply circuits comprising a MOSFET transistor. The invention is characterized in that it comprises: a sub-circuit for assisting with charging, a sub-circuit for assisting with discharging said MOSFET transistor, and a voltage-shifting sub-circuit.

Abstract: A switching audio amplifier and method of operation. The switching audio amplifier comprises a voltage supply selector coupling a power supply input to a first power supply voltage; a switching circuit generating a drive signal for a loudspeaker by modulating the power supply input based on a modulation signal; a pulse generator receiving an audio input signal and outputting the modulation signal based on the audio input signal and the voltage of the power supply input; and a supply voltage monitor. The supply voltage monitor is configured to increase the voltage of the power supply input by causing the voltage supply selector to couple the power supply input to a second power supply voltage responsive to the modulation signal exceeding the first threshold, and the supply voltage monitor preventing the voltage supply selector from reducing the voltage of the power supply input for a first time period.

Abstract: A class-D amplifier having an output driver with a first, second, and third driver, the output driver having a first output coupled to the first and third drivers, a second output coupled to the second driver; a sensing resistor coupled in series between the first driver and the first output; and a pulse width modulation (PWM) controller coupled to the inputs of the drivers and configured to receive an audio input signal; control a PWM generator to generate a first pulse signal and a second pulse signal based on the audio input signal and a power supply input; determine a voltage drop across the sensing resistor; and, responsive to the voltage drop being greater than a threshold, sequence control of the first pulse signal to the first driver and switch a voltage at the first driver to an increased voltage based on the voltage drop.

Abstract: A method of manufacturing a travelling wave parametric amplifier (TWPA) includes forming a superconducting junction on a substrate. Trenches are etched away through a metal surface and into a layer of dielectric material. The trenches define a plurality of fingers positioned in an interdigitated arrangement of capacitors defined by a metal and a dielectric material that remains from the etched away metal surface and the layer of dielectric material.

Abstract: A power amplifier circuit 10 includes amplifiers 102 and 103, bias circuits 1023 and 1033, and a control circuit 106 that controls the bias circuits 1023 and 1033. When the power amplifier circuit 10 operates in a low power mode, the control circuit 106 controls the bias circuit 1023 and the bias circuit 1033 such that a bias current or voltage is supplied to the amplifier 102 and a bias current or voltage is not supplied to the amplifier 103. When the power amplifier circuit 10 operates in a high power mode in which an output power is higher than an output power in the low power mode, the control circuit 106 controls the bias circuit 1023 and the bias circuit 1033 such that a bias current or voltage is supplied to the amplifier 102 and a bias current or voltage is supplied to the amplifier 103.

Abstract: Examples of amplifier circuitry regulate a transconductance value (Gm) of operational transconductance amplifiers (OTAs) in the amplifier to be approximately the same, which value is based on a supply voltage and a reference voltage applied to a reference OTA and the internal resistance of the reference OTA. The reference OTA generates an output current based on Gm and the reference voltage, which current is compared to current generated by the supply voltage and internal resistance of the reference OTA. A tail current transistor of each of the reference OTA and a main OTA that mirrors the Gm of the reference OTA provide a tail current feedback path by which Gm is regulated. Amplifying circuitry is coupled to the main OTA to receive current signals. Based on the received current signals, amplifying circuitry generates a differential output voltage signal. The gain of the amplifying circuitry is proportional to the supply voltage and remains relatively constant across process temperature variations.

Abstract: A resistance device (100) includes a field-effect transistor (TN) and a voltage applying circuit (1). The voltage applying circuit (1) applies a control voltage (Vgs) between the gate and source of the field-effect transistor (TN) according to a temperature (T) to control a resistance value (R) between the drain and source of the field-effect transistor (TN). The control voltage (Vgs) is a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs0). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T1).

Abstract: A circuit may include a two-stage feedforward compensated operational transconductance integrated amplifier, and the two-stage feedforward compensated operational transconductance integrated amplifier may include an input terminal, an output terminal, a signal path between the input terminal and the output terminal, the signal path comprising a first signal path gain stage and a second signal path gain stage, and ripple rejection circuitry coupled between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage.

Abstract: Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

Abstract: A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.

Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Abstract: An audio signal modulation and amplification circuit includes a common-mode electric potential controller, a carrier generator, and channel circuits. The common-mode electric potential controller is configured to generate one or more first common-mode electric potentials and second common-mode electric potentials. The carrier generator is adapted to receive the first common-mode electric potential to generate a carrier signal. Each of the channel circuits includes a filter, a comparison circuit, and a driving circuit. The filter is adapted to filter an input signal and generate a filtered signal based on a corresponding one of the second common-mode electric potentials. The comparison circuit is configured to compare the potential of the carrier signal with the potential of the filtered signal to generate a pulse-width modulation signal. The driving circuit is configured to be turned on or off in response to the pulse-width modulation signal to output a load driving signal.

Abstract: An amplifier circuit includes an input terminal, an output terminal, an amplifier including a first transistor and a second transistor that are connected in parallel, a first capacitor, and a second capacitor, and an inductor. Each of the first transistor and the second transistor has a gate connected to the input terminal, a source connected to ground, and a drain connected to the output terminal. The inductor is provided between the input terminal and a node of parallel connection of the first transistor and the second transistor on the side of the input terminal. The first capacitor is arranged in a path connecting the node and the gate of the first transistor, the second capacitor is arranged in a path connecting the node and the gate of the second transistor, and the capacitance of the first capacitor differs from the capacitance of the second capacitor.