Patents Examined by Hieu P Nguyen
  • Patent number: 11929717
    Abstract: An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahadevan Shankara Venkiteswaran, Arun Singh, Jofin Vadakkeparasseril Joseph
  • Patent number: 11923813
    Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaik Asif Basha, Mohit Chawla, Jasjot Singh Chadha
  • Patent number: 11923807
    Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 5, 2024
    Assignee: pSemi Corporation
    Inventors: Parvez H. Daruwalla, Yucheng Tong, Jonathan James Klaren
  • Patent number: 11909362
    Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (?) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Cirrus Logic Inc.
    Inventor: John Paul Lesso
  • Patent number: 11909359
    Abstract: An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 20, 2024
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Jean-Marc Mourant
  • Patent number: 11909364
    Abstract: Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 20, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventor: Katsuyuki Yasukouchi
  • Patent number: 11901814
    Abstract: An adaptive DC-DC boost converter arrangement and an electronic circuit including such an arrangement are provided. The arrangement includes a circuit board with a plurality of electronic components mounted thereon, implementing an adaptive DC-DC boost converter circuit and a boost decoupling capacitor. The adaptive DC-DC boost converter circuit comprises a DC-DC boost converter having a converter set value input, a boost supply input, and a boost voltage output, and an adaptive DC-DC boost control unit having a control input and a control output. An acoustical noise suppression filter is present having a filter input connected to the control output of the adaptive DC-DC boost control unit and a filter output connected to the converter set value input of the DC-DC boost converter.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 13, 2024
    Inventors: Lutsen Dooper, Han Martijn Schuurmans, Maarten Wilhelmus Henricus Marie Dommelen Van, Bernardus Henricus Krabbenborg, Ivo Johannes Petrus Moolenaar
  • Patent number: 11901866
    Abstract: An amplifier circuit, which has a first output terminal and a second output terminal, includes a first charge-steering amplifier, a second charge-steering amplifier, a first switch, and a second switch. The first charge-steering amplifier includes a first input terminal, a second input terminal, a first capacitor, and a second capacitor, and is used for amplifying a first input signal in a first operation period. The second charge-steering amplifier includes a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor, and is used for amplifying a second input signal in a second operation period. The first capacitor and the second capacitor charge during the first operation period and discharge during the second operation period.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 11894808
    Abstract: Systems and methods including variable power amplifier bias impedance are disclosed. In one aspect, there is provided a power amplifier system including a bias circuit configured to receive a bias voltage and generate a bias signal and a power amplifier stage configured to receive an input radio frequency (RF) signal and generate an output RF signal. The power amplifier system may also include a bias impedance component operatively coupled between the bias circuit and the power amplifier stage. The bias impedance is component configured to receive a control signal and adjust an impedance value of the bias impedance component in response to the control signal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 6, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11894812
    Abstract: The present disclosure relates to a kinetic inductance parametric amplifier that comprises an input port arranged to receive a pump tone, a DC bias and input signal; an output port arranged to provide an amplified version of the input signal; a tunable stepped-impedance assembly arranged to attenuate and/or filter predetermined frequency bands; and a high kinetic inductance line. The tunable stepped-impedance assembly is tuned at a frequency that allows for the amplifier to resonate at a predetermined frequency and a pump tone with a frequency higher than the input signal and a DC biasing signal to be transmitted to the high kinetic inductance line.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 6, 2024
    Assignee: SILICON QUANTUM COMPUTING PTY LIMITED
    Inventors: Jarryd Pla, Mykhailo Savytskyi
  • Patent number: 11881827
    Abstract: One illustrative high bandwidth transimpedance amplifier includes a distributed amplifier having multiple transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to the input signal's current. An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from a final node of the input signal line via a feedback impedance.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 23, 2024
    Assignee: Credo Technology Group Limited
    Inventor: Yida Duan
  • Patent number: 11881828
    Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 23, 2024
    Assignee: pSemi Corporation
    Inventors: Jing Li, Emre Ayranci, Miles Sanner
  • Patent number: 11881824
    Abstract: A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 23, 2024
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Tim Boescke
  • Patent number: 11876490
    Abstract: Described embodiments include an integrated circuit for temperature gradient compensation of a bandgap voltage. A bandgap core circuit has a bandgap feedback input, a bandgap adjustment input and a bandgap reference output. A resistor is coupled between the bandgap adjustment input and a ground terminal. An offset and slope correction circuit has an offset correction output that is coupled to the bandgap adjustment input. A signal at the offset correction output is trimmed at an ambient temperature. A thermal error cancellation (TEC) circuit has a TEC output coupled to the bandgap adjustment input. The TEC circuit includes first and second temperature sensors that are located apart from each other. A signal at the TEC output is responsive to temperatures at the first and second temperature sensors. An amplifier has an amplifier input and an amplifier output. The amplifier input is coupled to the bandgap reference output.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Shylaja Krishnan, Akshay Yashwant Jadhav, Tallam Vishwanath
  • Patent number: 11876493
    Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 16, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Subbarao Surendra Chakkirala, Sherif Galal, Earl Schreyer
  • Patent number: 11870405
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 9, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11870395
    Abstract: The present invention provides a detection circuit for a connection impedance and an electronic device. The detection circuit includes: a detection operational amplifier module, wherein the detection operational amplifier module includes: a first buffer, a switch unit, and a main operational amplifier; a first input terminal of the first buffer is connected to a first acquisition electrode through a first front-end circuit, an output terminal of the main operational amplifier is connected to a back-end circuit, and an output terminal of the first buffer is connected to a second input terminal of the first buffer; a first terminal of the switch unit is directly or indirectly connected to the first front-end circuit, and a second terminal of the switch unit is connected to the back-end circuit; and the switch unit is configured to: control the first front-end circuit to be directly connected to the back-end circuit, to form a straight-through channel.
    Type: Grant
    Filed: July 18, 2021
    Date of Patent: January 9, 2024
    Assignee: SHANGHAI YAOHUO MICROELECTRONICS Co., Ltd.
    Inventor: Lei Huang
  • Patent number: 11870400
    Abstract: A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 9, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Yi-Kuang Chen
  • Patent number: 11863135
    Abstract: A Class D power amplification modulation system for self-adaptive adjustment of an audio signal is provided, including an amplification circuit module, a pulse width modulation (PWM) circuit module connected to the amplification circuit module, a frequency detection circuit module, a carrier generator module connected to the frequency detection circuit module, an amplitude detection circuit module, a direct current (DC) potential adjustment module connected to the amplitude detection circuit module, and a drive circuit module. A method, a device, a processor, and a computer-readable storage medium are also provided. The characteristics of the circuit in the signal time domain and frequency are improved by simultaneously controlling the amplitude and the frequency of the audio signal, to minimize power consumption of signals with different amplitudes and frequencies, and to improve EMI performance, or to balance the circuit power consumption and EMI characteristics.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: CRM ICBG (WUXI) CO., LTD.
    Inventors: Xu Zhou, Hangjuan Jia, Dianjun Zhang, Fan Yang
  • Patent number: 11855592
    Abstract: A switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: John L Melanson