Abstract: An apparatus and method for determining signals representative of events in the environment of a reactive transducer while being driven by a switching amplifier is disclosed. While the switching amplifier is in a zero voltage state, a signal capture circuit that is also in a zero voltage state is connected to the transducer for a relatively brief period of time during which a measurement is made of the residual current flow due to the inductance of the transducer. A prediction of the output signal is then subtracted from the signal measured across the transducer, reducing the overall range of the signal and increasing the relative size of the back-EMF signal compared to any remaining output signal. If desired, conventional echo cancellation can then be performed. The back-EMF signal can then be subjected to further processing by an analog-to-digital converter as known in the art.

Abstract: A nuclear magnetic resonance (NMR) power supply system and method are disclosed. The architecture adopts a two-stage topology to reduce the required capacitance by over ten times, leading to a four-fold improvement in power density. The first stage is an isolated converter that only supplies average power, therefore input filter and transformer sizes can be reduced. The second stage is a fast response DC-DC converter followed by a RF transmitter to produce a pulsed RF signal, so that the mid-point voltage after the first stage can be allowed to droop considerably, leading to much smaller sized capacitors. These and other embodiments enforce the isolated converter to only transfer average power, which reduces the power rating and the volume of the system's transformer.

Abstract: An amplifier circuit includes a circuit path of serially connected complementary type transistors. First and second feedback loops include a loop amplifier, the transistors of the circuit path and a corresponding resistor.

Abstract: An amplifier circuit has an output stage, a first current source, a second current source, a third current source, a fourth current source, and a voltage clamping voltage. The output stage has a first P-type transistor and a first N-type transistor. The voltage clamping circuit receives a first bias voltage and a second bias voltage, and has a first end and a second end. When a second input current is positive current and the input current is a negative current or a zero current, the first end provides a first clamping voltage greater than the first bias voltage to a gate of the first P-type transistor. When the first input current is positive and the second input current is a negative current or zero current, the second end provides a second clamping voltage lower than the second bias voltage to a gate of the first N-type transistor.

Abstract: The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals.

Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.

Abstract: A protection circuit comprises a first transistor, a comparator, a second transistor, and a third transistor. The first transistor has a gate connected to an input terminal and configured to pass a drain current based on a potential at the input terminal. The comparator has a non-inverting terminal to which a source of the first transistor is connected and an inverting terminal to which a reference voltage is applied. The second transistor has a gate to which an output of the comparator is applied, a source connected to a power supply voltage, and a drain connected to the input terminal. The third transistor has a gate to which a predetermined voltage is applied, a drain connected to the gate of the second transistor, and a source connected to the drain of the input transistor.

Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.

Abstract: A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

Abstract: Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

Abstract: An adaptive sample and hold circuit for signal amplifier range selection is presented. The adaptive sample and hold circuit has an input for receiving an input signal and an output for providing a sample-and-hold-voltage. It also includes a sample-and-hold-capacitor to generate the sample-and-hold-voltage from the input signal, and a range detector. The range detector is adapted to identify a range of the input signal and to adjust a voltage at the sample-and-hold-capacitor based on the range of the input signal to maintain the sample-and-hold-voltage within a predetermined voltage span.

Abstract: An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

Abstract: According to one embodiment, a class-D amplifier including: a PWM modulator that outputs a PWM modulation signal in response to an input signal; and a drive circuit that amplifies the PWM modulation signal, and supplies it to an output end. The drive circuit includes: a first output transistor whose main current path is connected between a power source supplying end and the output end; a second output transistor having a size larger than a size of the first output transistor; and a resistance element that is connected between the main current path of the first output transistor and the output end.

Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

Abstract: A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks.

Abstract: A two-stage differential amplifier with cross-coupled compensation capacitors. The differential amplifier includes first amplifier circuitry receiving a differential input voltage and presenting first and second intermediate outputs. The amplifier further includes a second amplifier stage with a first leg having an input coupled to the second intermediate output of the first amplifier circuitry, and a second leg having an input coupled to the first intermediate output of the first amplifier circuitry. A compensation capacitor is provided for each leg of the second amplifier stage, each coupled between the output of that amplifier leg and its input. A first cross-coupled capacitor is coupled between the output of the first amplifier leg to the input of the second amplifier leg, and a second cross-coupled capacitor is coupled between the output of the second amplifier leg and the input of the first amplifier leg.

Abstract: A supply voltage circuit for reducing in-rush battery current in an envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC includes an ET voltage circuit configured to generate a time-variant ET voltage, which includes an offset voltage, in multiple time intervals based on a supply voltage. In some cases, the offset voltage and the supply voltage may both need to be increased or decreased as the time-variant ET voltage increases or decreases. As the offset voltage and the supply voltage increase or decrease, an excessive in-rush battery current may result in a reduced battery life. In this regard, a supply voltage circuit is configured to help the ETIC to adapt the supply voltage on a per-symbol basis. As a result, it is possible to reduce the in-rush battery current in the ETIC while still allowing the time-variant ET voltage to change in a timely manner.