Patents Examined by Hieu P Nguyen
  • Patent number: 10476452
    Abstract: Adjustable load line amplifier circuits may comprise a power amplifier that has a signal input terminal to receive an input signal, a powered signal output terminal to be coupled to a load that has changing impedances, and a transistor array of transistor cells operatively coupled in parallel between the signal input terminal and the powered signal output terminal such that the transistor cells are independently configured to amplify the input signal present at the signal input terminal and effect a selected load line impedance of the transistor array that corresponds to at least one of the changing impedances of the load. The transistor array controller may be configured to effect the selected load line impedance by selectively activating one or more of the transistor cells and/or providing the transistor cells with a selectable operating voltage.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 12, 2019
    Assignee: The Boeing Company
    Inventors: Alireza Shapoury, Brian Kenneth Kormanyos
  • Patent number: 10469031
    Abstract: An envelope detecting circuit is for generating an envelope signal of an input RF signal as described. The envelope detecting circuit includes an input terminal, an output terminal, a balun, a transistor, and an integrating circuit. The transistor, which is operated in the class B or the class C mode, receives an input signal from the balun, amplifies the input signal, and outputs an amplified signal. The integrating circuit, which is provided between the transistor and the output terminal, provides a series circuit of a resistor and a capacitor between the bias supply and ground. The transistor receives the bias through the resistor. The capacitor holds bottom levels of the amplified signal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 5, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Osamu Anegawa
  • Patent number: 10461702
    Abstract: The present invention provides an amplifier circuit, wherein the amplifier circuit includes an operational amplifier and a feedback path. The operational amplifier has an input terminal and an output terminal, and is arranged for receiving an input signal to generate an output signal. The feedback path is coupled between the input terminal and the output terminal of the operational amplifier, wherein the feedback path comprises at least two poly resistors, and a depletion region of at least one of the two poly resistors is biased by the output signal generated by the operational amplifier.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 29, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tsun-Yuan Fan, Tze-Chien Wang
  • Patent number: 10461707
    Abstract: An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vadim Valerievich Ivanov
  • Patent number: 10454438
    Abstract: A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a chopping modulator circuit that continuously swaps tail current sources between the transconductors. This tail current swapping reduces the contribution to the CFIA's gain error caused by random mismatch between the tail currents of the input and feedback transconductors. The modulator circuit operates on a clock cycle to periodically swap the tail current sources. As a result, even if the tail currents are mismatched, on average the tail currents (transconductor gains) will approximately equal out, and the contribution of the tail current difference to the gain error is canceled out.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 22, 2019
    Assignee: Microchip Technology Incorporated
    Inventors: Serban Motoroiu, Jim Nolan
  • Patent number: 10447209
    Abstract: Embodiments of the disclosure generally relate to a method and device for improving the efficiency of a power amplifier. The apparatus comprising: a harmonic generator, configured to generate one or more harmonic according to an output signal of a power amplifier; a harmonic feedback device, configured to inject the harmonic generated by the harmonic generator to an input terminal of the power amplifier; and a harmonic eliminator, configured to eliminate the harmonic in the output signal of the power amplifier. According to embodiments of the disclosure, the efficiency of power amplifier can be improved without degrading the linearity.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 15, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Zhancang Wang
  • Patent number: 10439563
    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 8, 2019
    Assignee: pSemi Corporation
    Inventors: Tsuyoshi Takagi, Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk
  • Patent number: 10439562
    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 8, 2019
    Assignee: pSemi Corporation
    Inventors: Ikumi Tokuda, Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk
  • Patent number: 10439565
    Abstract: A low noise amplifier (LNA) device includes a first transistor on a semiconductor on insulator (SOI) layer. The first transistor includes a source region, a drain region, and a gate. The LNA device also includes a first-side gate contact coupled to the gate. The LNA device further includes a second-side source contact coupled to the source region. The LNA device also includes a second-side drain contact coupled to the drain region.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Sinan Goktepeli
  • Patent number: 10439566
    Abstract: A power amplifier circuit includes a differential to single-ended converter, a gain stage circuit, a driver stage circuit, and an output stage circuit connected in series, and a bias circuit connected to a bias voltage port of the gain stage circuit for adjusting a bias voltage of the gain stage circuit. The bias voltage is adjustable to ensure low power consumption, improve the efficiency of the power amplifier circuit and prevent process, voltage and temperatures from affecting the performance of the power amplifier circuit.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 8, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Hao Sun
  • Patent number: 10432153
    Abstract: The present invention reveals a new biasing method which can be used in solid state audio power amplifier design despite of the Class of operation. The proposed biasing technology relies only on traditional electrical feedback to build up and maintain the desired biasing current and doesn't need thermal coupling or thermal tracking techniques in order to overcome power transistor device's temperature dependent input-output characteristics as required by traditional approach. An ingenious current sensing and amplification circuit is devised in order to generate an voltage output which is only corresponding to the quiescent biasing current of the output stage. This voltage output is then used as an representative of the power stage biasing current to be regulated by a feedback loop comprising a traditional voltage multiplier, the output stage and the aforementioned current sensing and amplification circuit.
    Type: Grant
    Filed: March 4, 2018
    Date of Patent: October 1, 2019
    Inventor: Zhenwu Wang
  • Patent number: 10432155
    Abstract: A bias current generator is disclosed that include an operational amplifier that is self-biased during an inactive period with a bias current to bias a gate of an output transistor. Since the inactive period bias is close to an active period bias applied to the gate of the output transistor during active operation of the bias current generator, the speed of transition from the inactive period to the active period is enhanced by the self-biasing of the operational amplifier.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 1, 2019
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventor: Pranav Kotamraju
  • Patent number: 10425041
    Abstract: Disclosed is a differential transimpedance amplifier (TIA). In the differential TIA, an input end of the first source follower is coupled to the first output end of a first differential amplification circuit. The output end of the first source follower is coupled to the second input end of a second differential amplification circuit with feedback and a first feedback resistor. The input end of a second source follower is coupled to the second output end of the first differential amplification circuit. The output end of the second source follower is coupled to the first input end of the second differential amplification circuit with feedback and a second feedback resistor. A photo diode and a dummy diode are coupled respectively to two input ends of the first differential amplification circuit.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 24, 2019
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Meng-Tong Tan
  • Patent number: 10425053
    Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 24, 2019
    Assignee: AVNERA CORPORATION
    Inventors: Garry N. Link, Eric King, Xudong Zhao, Wai Lee, Alexander C. Stange, Amit Kumar
  • Patent number: 10418952
    Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: NXP USA, INC.
    Inventors: Kumar Abhishek, Srikanth Jagannathan
  • Patent number: 10411662
    Abstract: Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Aleksey A. Lyalin, Taesong Hwang, Russ Alan Reisner, Nicholas Quinn Muhlmeyer
  • Patent number: 10404227
    Abstract: A quaternary/ternary modulation selecting circuit of an amplifier includes: a signal generating circuit, a detecting circuit, and a selecting circuit. The signal generating circuit is arranged to generate a ternary signal and a quaternary signal. The detecting circuit coupled to the signal generating circuit is arranged to generate a mode selecting signal according to at least the ternary signal. The selecting circuit coupled to the signal generating circuit and the detecting circuit is arranged to select and output one of the ternary signal and the quaternary signal to an output stage of the amplifier according to the mode selecting signal.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 3, 2019
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Szu-Chun Tsao, Deng-Yao Shih
  • Patent number: 10396734
    Abstract: Disclosed is a differential transimpedance amplifier. The differential transimpedance amplifier includes a common gate amplifier configured to receive an electrical signal from an input node, and a common source amplifier configured to have a feedback resistor and receive the electrical signal form the input node. An output signal of the common gate amplifier and an output signal of the common source amplifier form a differential signal pair. The common gate amplifier and the common source amplifier each includes a load having a transformer which removes an effect of parasitic capacitance.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 27, 2019
    Assignee: EWHA UNIVERSITY—INDUSTRY COLLABORATION FOUNDATION
    Inventor: Sung Min Park
  • Patent number: 10396765
    Abstract: A power amplifying apparatus includes a power circuit configured to generate operating power, a random pulse generation circuit configured to be supplied with the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time using an input radio frequency (RF) signal, and a charge pump circuit configured to be supplied with the operating power and to randomly perform a switching operation according to the pulse width modulation signal to generate a negative voltage.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jeong Hoon Kim, Hyun Paek, Jong Ok Ha
  • Patent number: 10396727
    Abstract: Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: August 27, 2019
    Assignee: CREE, INC.
    Inventors: Saurabh Goel, Richard Wilson, Haedong Jang