Patents Examined by Hieu P Nguyen
  • Patent number: 11894808
    Abstract: Systems and methods including variable power amplifier bias impedance are disclosed. In one aspect, there is provided a power amplifier system including a bias circuit configured to receive a bias voltage and generate a bias signal and a power amplifier stage configured to receive an input radio frequency (RF) signal and generate an output RF signal. The power amplifier system may also include a bias impedance component operatively coupled between the bias circuit and the power amplifier stage. The bias impedance is component configured to receive a control signal and adjust an impedance value of the bias impedance component in response to the control signal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 6, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11894812
    Abstract: The present disclosure relates to a kinetic inductance parametric amplifier that comprises an input port arranged to receive a pump tone, a DC bias and input signal; an output port arranged to provide an amplified version of the input signal; a tunable stepped-impedance assembly arranged to attenuate and/or filter predetermined frequency bands; and a high kinetic inductance line. The tunable stepped-impedance assembly is tuned at a frequency that allows for the amplifier to resonate at a predetermined frequency and a pump tone with a frequency higher than the input signal and a DC biasing signal to be transmitted to the high kinetic inductance line.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 6, 2024
    Assignee: SILICON QUANTUM COMPUTING PTY LIMITED
    Inventors: Jarryd Pla, Mykhailo Savytskyi
  • Patent number: 11881827
    Abstract: One illustrative high bandwidth transimpedance amplifier includes a distributed amplifier having multiple transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to the input signal's current. An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from a final node of the input signal line via a feedback impedance.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 23, 2024
    Assignee: Credo Technology Group Limited
    Inventor: Yida Duan
  • Patent number: 11881828
    Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 23, 2024
    Assignee: pSemi Corporation
    Inventors: Jing Li, Emre Ayranci, Miles Sanner
  • Patent number: 11881824
    Abstract: A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 23, 2024
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Tim Boescke
  • Patent number: 11876490
    Abstract: Described embodiments include an integrated circuit for temperature gradient compensation of a bandgap voltage. A bandgap core circuit has a bandgap feedback input, a bandgap adjustment input and a bandgap reference output. A resistor is coupled between the bandgap adjustment input and a ground terminal. An offset and slope correction circuit has an offset correction output that is coupled to the bandgap adjustment input. A signal at the offset correction output is trimmed at an ambient temperature. A thermal error cancellation (TEC) circuit has a TEC output coupled to the bandgap adjustment input. The TEC circuit includes first and second temperature sensors that are located apart from each other. A signal at the TEC output is responsive to temperatures at the first and second temperature sensors. An amplifier has an amplifier input and an amplifier output. The amplifier input is coupled to the bandgap reference output.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Shylaja Krishnan, Akshay Yashwant Jadhav, Tallam Vishwanath
  • Patent number: 11876493
    Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 16, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Subbarao Surendra Chakkirala, Sherif Galal, Earl Schreyer
  • Patent number: 11870405
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 9, 2024
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11870395
    Abstract: The present invention provides a detection circuit for a connection impedance and an electronic device. The detection circuit includes: a detection operational amplifier module, wherein the detection operational amplifier module includes: a first buffer, a switch unit, and a main operational amplifier; a first input terminal of the first buffer is connected to a first acquisition electrode through a first front-end circuit, an output terminal of the main operational amplifier is connected to a back-end circuit, and an output terminal of the first buffer is connected to a second input terminal of the first buffer; a first terminal of the switch unit is directly or indirectly connected to the first front-end circuit, and a second terminal of the switch unit is connected to the back-end circuit; and the switch unit is configured to: control the first front-end circuit to be directly connected to the back-end circuit, to form a straight-through channel.
    Type: Grant
    Filed: July 18, 2021
    Date of Patent: January 9, 2024
    Assignee: SHANGHAI YAOHUO MICROELECTRONICS Co., Ltd.
    Inventor: Lei Huang
  • Patent number: 11870400
    Abstract: A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 9, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Yi-Kuang Chen
  • Patent number: 11863135
    Abstract: A Class D power amplification modulation system for self-adaptive adjustment of an audio signal is provided, including an amplification circuit module, a pulse width modulation (PWM) circuit module connected to the amplification circuit module, a frequency detection circuit module, a carrier generator module connected to the frequency detection circuit module, an amplitude detection circuit module, a direct current (DC) potential adjustment module connected to the amplitude detection circuit module, and a drive circuit module. A method, a device, a processor, and a computer-readable storage medium are also provided. The characteristics of the circuit in the signal time domain and frequency are improved by simultaneously controlling the amplitude and the frequency of the audio signal, to minimize power consumption of signals with different amplitudes and frequencies, and to improve EMI performance, or to balance the circuit power consumption and EMI characteristics.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: CRM ICBG (WUXI) CO., LTD.
    Inventors: Xu Zhou, Hangjuan Jia, Dianjun Zhang, Fan Yang
  • Patent number: 11855592
    Abstract: A switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: John L Melanson
  • Patent number: 11855597
    Abstract: This application relates to circuitry for monitoring for instability of an amplifier. The amplifier (100) has a first signal path between an amplifier input (INN) and an amplifier output (VOUT) and a feedback path from the output to form a feedback loop with at least part of the first signal path. A comparator (212) has a first input configured to receive a first signal (INN) derived from a first amplifier node which is part of said feedback loop and a second input configured to receive a second signal (INP) derived from a second amplifier node which varies with the signal at the amplifier input but does not form part of said feedback loop. The comparator is configured to compare the first signal to the second signal and generate a comparison signal (COMP), wherein in the event of amplifier instability the comparison signal comprises a characteristic indicative of amplifier instability.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 26, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Sameer Baveja, Hamed Sadati
  • Patent number: 11845271
    Abstract: An electronic device inputs a voltage from each of a first and a second constant voltage sources, amplifies the inputted voltage, and converts the inputted voltage or a voltage amplified by an amplifier into a digital value. Using a first and a second digital values based on the inputted voltage, and a third and fourth digital values based on the inputted, amplified and converted voltage, an amplification factor of the amplifier and an offset voltage of the amplifier are calculated, and the amplifier is corrected based on the calculated amplification factor and offset voltage.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: December 19, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hideyuki Ueki, Shinya Ishikawa, Hironori Naka, Hiroyuki Takahashi, Yuta Shinsawatsu, Kotaro Kimoto
  • Patent number: 11848652
    Abstract: This application relates to circuitry for monitoring for instability of an amplifier. The amplifier (100) has a first signal path between an amplifier input (INN) and an amplifier output (VOUT) and a feedback path from the output to form a feedback loop with at least part of the first signal path. A comparator (212) has a first input configured to receive a first signal (INN) derived from a first amplifier node which is part of said feedback loop and a second input configured to receive a second signal (INP) derived from a second amplifier node which varies with the signal at the amplifier input but does not form part of said feedback loop. The comparator is configured to compare the first signal to the second signal and generate a comparison signal (COMP), wherein in the event of amplifier instability the comparison signal comprises a characteristic indicative of amplifier instability.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 19, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Sameer Baveja, Hamed Sadati
  • Patent number: 11848651
    Abstract: A switching amplifier system with a power supply, a pulse modulator configured to modulate an input signal into a pulse width modulation signal, a switching stage configured to generate an amplified output signal, and an error feedback signal configured to correct errors in the amplified output signal, where the input signal is comprised of at least one of an analog signal and a digital signal. A method of signal amplification comprising generating, by a pulse width modulator, a pulse width modulation signal, combining, by a switching stage, the input signal and the pulse width modulation signal to form an amplified output signal, and generating, by the switching stage, an error feedback signal, where the error feedback signal is configured to correct errors in the amplified output signal, and where the input signal is comprised of at least one of an analog signal and a digital signal.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: December 19, 2023
    Assignee: ADX Research, Inc.
    Inventors: Pallab Midya, Adip Kumar Dutta, Uma Ekambaram Iyer
  • Patent number: 11848649
    Abstract: An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhi Qi Huang, Wei Lu Chu
  • Patent number: 11843357
    Abstract: Methods and devices for clamping an output of an amplifier stage of an amplifier are presented. According to one aspect, a clamp sense circuit senses a voltage at a node of an internal stage of the amplifier. The clamp sense circuit senses a region of operation of the clamp circuit and correspondingly controls a current limiter that is introduced in the amplifier to limit a current through the internal stage of the amplifier. Limiting the current in turn causes limiting a current path from a clamp circuit through the output of the amplifier stage. According to another aspect, the clamp sense circuit is a replica of the amplifier stage of the amplifier, the output of the amplifier stage coupled to the clamp circuit, and an output of the replica decoupled from the clamp circuit.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: December 12, 2023
    Assignee: pSemi Corporation
    Inventor: Christopher C. Murphy
  • Patent number: 11843355
    Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 12, 2023
    Assignee: Raytheon Company
    Inventors: Bryan W. Kean, Eric J. Beuville, Ravi S. Kirschner
  • Patent number: 11837999
    Abstract: An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: December 5, 2023
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Rajdeep Mukhopadhyay, Euan Murphy, Matt Felder, Simon Quinn