Patents Examined by Hieu P Nguyen
  • Patent number: 10656006
    Abstract: A sensing system with an AC feedback to the non-signal and non-biased terminal of the transducer. An impedance element, such as two anti-parallel diodes, are provided at the amplifier input, and the amplifier gain is negative and has a size sufficient to ensure that the input on the one terminal does not exceed the forward voltage of the diode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 19, 2020
    Assignee: Sonion Nederland B.V.
    Inventor: Adrianus Maria Lafort
  • Patent number: 10658984
    Abstract: A differential amplifier circuit includes a differential pair including a first field-effect transistor (FET) and a second FET, a first current source that generates a current which flows in the first FET and the second FET, and an output circuit that outputs an output voltage corresponding to a difference between a gate voltage of the first FET and a gate voltage of the second FET in accordance with an operation of the differential pair. A back gate of the first FET is connected to a gate of the first FET, and a back gate of the second FET is connected to a gate of the second FET. A first feedback voltage corresponding to the output voltage is input to the gate of the second FET.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 19, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yusuke Shimamune
  • Patent number: 10651811
    Abstract: A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: May 12, 2020
    Assignee: NXP USA, Inc.
    Inventors: Douglas A. Garrity, Mariam Hoseini, Mohammad N. Kabir, Brandt Braswell
  • Patent number: 10644664
    Abstract: An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jikai Chen, Gerd Schuppener, Yanli Fan
  • Patent number: 10642430
    Abstract: A differential circuit is provided. The differential circuit comprises a plurality of electrodes comprising at least a middle electrode, wherein the middle electrode is directly adjacent to a first electrode and a second electrode of the plurality of electrodes; a plurality of amplifiers, coupled to the plurality of electrodes; and at least a buffer, coupled between the middle electrode and at least one amplifier of the plurality of amplifiers.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 5, 2020
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Tzu-Li Hung, Fu-Chiang Yang, Ya-Nan Wen
  • Patent number: 10637418
    Abstract: A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 28, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Rami Khatib, Faisal Hussien
  • Patent number: 10637408
    Abstract: An envelope tracking (ET) voltage tracker circuit and related power management circuit are provided. In examples discussed herein, an amplifier circuit(s) is configured to amplify a radio frequency (RF) signal(s) based on an ET modulated voltage provided by an ET voltage tracker circuit(s). The ET voltage tracker circuit(s) includes amplifier circuitry, which operates based on an ET target voltage and a bias current to generate the ET modulated voltage. However, the ET modulated voltage may deviate from the ET target voltage from time to time due to cross over distortions. In this regard, the ET voltage tracker circuit includes a bias modulation circuit to dynamically determine the cross over distortion and adjust the bias current to reduce deviations of the ET modulated voltage. As a result, the ET modulated voltage can track the ET target voltage more closely, thus helping to improve linearity performance and efficiency of the amplifier circuit(s).
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 28, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay
  • Patent number: 10637416
    Abstract: A trans-impedance amplifier (TIA) includes a first circuit, a second circuit, and a third circuit. Both the first circuit and the second circuit are coupled to a current source, an operational amplifier, and the third circuit. The first circuit is configured to receive a first current, provide a third voltage to the third circuit, perform shape filtering on the first current, and convert the shape filtered first current to a first voltage for output. The second circuit is configured to receive a second current, provide a fourth voltage to the third circuit, perform shape filtering on the second current, and convert the shape filtered second current to a second voltage for output. The third circuit is configured to cooperate with the first circuit and the second circuit in performing shape filtering. The operational amplifier is configured to provide a small-signal virtual ground point to the first circuit.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 28, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Baoyue Wei, Yuemiao Di
  • Patent number: 10630242
    Abstract: A Doherty amplifier has a first amplifier path that includes a first amplifier, a second amplifier path that includes a second amplifier, a power divider, and a short-circuited stub. The power divider receives an RF signal and divides the RF signal into first and second input signals. The power divider includes first and second power divider outputs that produce the first and second input signals, respectively. The short-circuited stub is coupled between the first power divider output and the first amplifier or between the second power divider output and the second amplifier. The first and second amplifier paths are characterized by first and second frequency-dependent insertion phases, respectively. A slope of the first or second frequency-dependent insertion phase is altered by the short-circuited stub. The power divider produces the first and second input signals with a quadrature phase shift.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Roy McLaren
  • Patent number: 10630248
    Abstract: A low-noise amplifier system is disclosed. The low-noise amplifier system includes a low-noise amplifier having an input node and an output node in a receive path and a capacitance equalization network coupled to the output node. Compensation capacitance of the capacitance equalization network sums with non-linear capacitance of the low-noise amplifier such that a total capacitance at the output node varies by no more than ±5% over an output voltage range within voltage headroom limits of the low-noise amplifier for a given supply voltage of the low-noise amplifier. In at least some exemplary embodiments, the compensation capacitance of the capacitance equalization network is a function of output signal voltage at the output node.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Marcus Granger-Jones, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10630244
    Abstract: A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 21, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Janakan Sivasubramaniam, Rami Khatib
  • Patent number: 10630247
    Abstract: A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 21, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jong Ok Ha, Jeong Hoon Kim, Youn Suk Kim
  • Patent number: 10615759
    Abstract: Methods and systems for accurate gain adjustment of a transimpedance amplifier using a dual replica and servo loop is disclosed and may include, in a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, and a third TIA, each comprising a configurable feedback impedance, and a control loop, where the control loop comprises a gain stage with inputs coupled to outputs of the first and second TIAs and an output coupled to the configurable feedback impedance of the second and third TIAs: configuring a gain level of the first TIA by configuring its feedback impedance, configuring a gain level of the third TIA by configuring a reference current applied to an input of the first TIA, and amplifying a received electrical signal to generate an output voltage utilizing the third TIA. The reference current may generate a reference voltage at one of the inputs of the gain stage.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 7, 2020
    Assignee: Luxtera, Inc.
    Inventors: Stefan Barabas, Joseph Balardeta, Simon Pang, Scott Denton
  • Patent number: 10615762
    Abstract: Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shota Ishihara
  • Patent number: 10608594
    Abstract: In a Doherty amplifier including a carrier amplifier (6) and a peaking amplifier (8) connected in parallel with each other, a compensation circuit (9) for causing an impedance seen from an output end (9a) of the compensation circuit (9) toward the peaking amplifier (8) to be open within a used frequency range and compensating for frequency dependence of an impedance seen from an output of a combiner (10) toward the combiner (10) in a state in which the peaking amplifier (8) is not operating is arranged between the peaking amplifier (8) and the combiner (10). This achieves a wider bandwidth without making the circuit larger in size and more complicated.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 31, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Komatsuzaki, Shintaro Shinjo, Keigo Nakatani, Shohei Imai
  • Patent number: 10601381
    Abstract: Monolithic microwave integrated circuits (MMICs) with phase tuning are disclosed. A MMIC structure may include a MMIC amplifier with electrically coupled input and output lines. The MMIC structure may further include an adjustable cover over the MMIC amplifier that includes at least one portion that can be adjusted closer to or farther away from either the input or output lines. In this manner, a signal capacitance between the adjustable cover and the input or output lines is adjustable, and accordingly, a signal phase of the MMIC structure may be tuned. A spatial power-combining device may include a plurality of amplifier assemblies, wherein each amplifier assembly includes a MMIC amplifier with an adjustable cover. In this manner, the plurality of amplifier assemblies may be phase-tuned to a target value.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Soack Yoon, Ankush Mohan, Dan Denninghoff
  • Patent number: 10601386
    Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 24, 2020
    Assignee: Rafael Microelectronics, Inc.
    Inventors: Meng-Ping Kan, Kuan-Ming Chen, Benjamin Chiang, Tzy-Yun Wang
  • Patent number: 10594278
    Abstract: An amplifier circuit. In some embodiments, the amplifier circuit includes: a telescopic amplifier, and a common mode feedback amplifier. The telescopic amplifier has a first signal input, a second signal input, a first output, a second output, a common mode feedback input, a first pole-splitting capacitor, and a second pole-splitting capacitor. The common mode feedback amplifier has an output connected to the common mode feedback input of the telescopic amplifier. The first pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the first output of the telescopic amplifier, and the second pole-splitting capacitor is connected between the common mode feedback input of the telescopic amplifier and the second output of the telescopic amplifier.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Vaibhav Tripathi
  • Patent number: 10594273
    Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 17, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shingo Yanagihara
  • Patent number: 10587235
    Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudheer Prasad