Patents Examined by Hoang-Quan Ho
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Patent number: 9637834Abstract: A method for fabricating an electrically programmable fuse structure is provided. The method includes providing a substrate. The method also includes forming an anode and a cathode on the substrate. Further, the method includes forming a fuse between the anode and the cathode and having an anode-connecting-end connecting with the anode and a cathode-connecting-end connecting with the cathode over the substrate. Further, the method also includes forming a compressive stress region in the cathode-connecting-end, wherein the anode-connecting-end has a tensile stress region.Type: GrantFiled: December 10, 2015Date of Patent: May 2, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Zhenghao Gan
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Patent number: 9627355Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.Type: GrantFiled: May 2, 2016Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 9627310Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.Type: GrantFiled: April 11, 2012Date of Patent: April 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
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Patent number: 9620671Abstract: A nitride semiconductor light emitting element is provided with: a substrate; a buffer layer that is provided on the substrate; a base layer that is provided on the buffer layer; an n-side nitride semiconductor layer that is provided on the base layer; an MQW light emitting layer that is provided on the n-side nitride semiconductor layer; and a p-side nitride semiconductor layer that is provided on the MQW light emitting layer. An x-ray rocking curve half-value width ? (004) with respect to a (004) plane, i.e., the crystal plane of the nitride semiconductor, is 40 arcsec or less, or the x-ray rocking curve half-value width ? (102) with respect to a (102) plane is 130 arcsec or less, and the rate P (80)/P (25) between light output P (25) at 25° C. and light output P (80) at 80° C. with a same operating current is 95% or more.Type: GrantFiled: May 15, 2013Date of Patent: April 11, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroshi Nakatsu, Tomoya Inoue, Kentaro Nonaka, Toshiaki Asai, Tadashi Takeoka, Yoshihiko Tani
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Patent number: 9620471Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.Type: GrantFiled: May 27, 2015Date of Patent: April 11, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Martin Standing, Robert J. Clarke
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Patent number: 9620607Abstract: A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region.Type: GrantFiled: December 4, 2014Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Chin-Chi Wang
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Patent number: 9608049Abstract: An organic light emitting diode (OLED) display includes a flexible substrate, a barrier layer disposed on the flexible substrate, and an organic light emitting diode disposed on the barrier layer. The barrier layer includes a plurality of metal layers and a plurality of insulation layers in which the metal layers and the insulation layers are alternatively stacked with each other on the flexible substrate.Type: GrantFiled: October 1, 2014Date of Patent: March 28, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Jusuck Lee
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Patent number: 9598280Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.Type: GrantFiled: November 10, 2014Date of Patent: March 21, 2017Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Dwight L. Daniels, Darrel R. Frear, Stephen R. Hooper
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Patent number: 9595586Abstract: A semiconductor device, includes an n-type semiconductor layer provided with a first semiconductor layer with a low electron carrier concentration and a second semiconductor layer with a high electron carrier concentration, an electrode that is in Schottky-contact with a surface of the first semiconductor layer, and an ohmic electrode formed on a surface of the second semiconductor layer. The n-type semiconductor layer is formed of a Ga2O3-based single crystal. The first semiconductor layer has an electron carrier concentration Nd based on reverse withstand voltage VRM and electric field-breakdown strength Em of the Ga2O3-based single crystal.Type: GrantFiled: July 12, 2016Date of Patent: March 14, 2017Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Patent number: 9590158Abstract: A light emitting device, includes: a package equipped with a lead having an upper surface and a lower surface, and a metal board and a plating layer, the upper surface including a mounting portion, the metal board whose main component is copper, the plating layer including a first plating layer and a second plating layer which are provided on the lower surface of the metal board, the first plating layer containing silver and nickel and being formed on the edge of the metal board, and the second plating layer containing no nickel and being formed on at least part of a region below the mounting portion, a molded resin that holds the lead so that the lower face of the lead is exposed to the outside; a light emitting element mounted on the mounting portion; and a sealing member that seals the light emitting element.Type: GrantFiled: December 18, 2015Date of Patent: March 7, 2017Assignee: NICHIA CORPORATIONInventor: Tomohide Miki
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Patent number: 9589979Abstract: A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.Type: GrantFiled: November 19, 2014Date of Patent: March 7, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Shih-Ping Hong
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Patent number: 9583470Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.Type: GrantFiled: December 19, 2013Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande
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Patent number: 9570590Abstract: A method is provided for forming an integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs. Initially, a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge) is formed. The SiGe layer is recessed to form a recessed SiGe layer in the n-type region while leaving an intact SiGe layer in the p-region. A Si layer consisting essentially of Si is formed on the recessed SiGe layer. The Si layer and recessed SiGe layer are patterned to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion. The intact SiGe layer in the p-region is patterned to form an intact SiGe fin. The recessed SiGe fin portion in the n-region is selectively oxidized utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.Type: GrantFiled: December 10, 2015Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin, Tenko Yamashita
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Patent number: 9553202Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.Type: GrantFiled: September 17, 2014Date of Patent: January 24, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
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Patent number: 9543513Abstract: A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of Xp(GeaSb(1-a-b)Teb)(1-p), wherein an atomic concentration of the impurities X is in a range of 0<p?0.2, an atomic concentration of Ge is in a range of 0.05?a<0.19, and an atomic concentration of Te is in a range of 0.42?b?0.56.Type: GrantFiled: December 10, 2015Date of Patent: January 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Hyung Kim, Jong-Uk Kim, Dong-Ho Ahn, Sung-Lae Cho
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Patent number: 9543219Abstract: A method of monitoring a temperature of a plurality of regions in a substrate during a deposition process, the monitoring of the temperature including: forming, in the monitored plurality of regions, a plurality of metal structures each with a different metal pattern density, where each metal pattern density corresponds to a threshold temperature at or above which metal voids and surface roughness are formed in the plurality of metal structures, and detecting metal voids and surface roughness in the plurality of metal structures to determine the temperature of the monitored plurality of regions.Type: GrantFiled: December 2, 2014Date of Patent: January 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Shawn A. Adderly, Samantha D. DiStefano, Mark J. Esposito, Jeffrey P. Gambino, Prakash Periasamy
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Patent number: 9515187Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.Type: GrantFiled: January 29, 2015Date of Patent: December 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin
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Patent number: 9515228Abstract: A face-up-type Group III nitride semiconductor light-emitting device includes a growth substrate, an n-type layer, a light-emitting layer, a p-type layer, an n-electrode including a bonding portion and a wiring portion, a p-electrode including a bonding portion and a wiring portion, and a first insulating film. The n-type layer, the light-emitting layer, and the p-type layer are sequentially stacked on the growth substrate, and the n-electrode and the p-electrode are formed on the first insulating film. A groove having a depth extending from a top surface of the p-type layer to the n-type layer is formed in at least one region selected from a region directly below the wiring portion of the n-electrode and a region directly below the wiring portion of the p-electrode. The wiring portion, which is formed in the groove, is located at a level lower than that of the light-emitting layer.Type: GrantFiled: December 1, 2014Date of Patent: December 6, 2016Assignee: TOYODA GOSEI CO., LTD.Inventors: Shingo Totani, Masashi Deguchi, Naoki Nakajo
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Patent number: 9516432Abstract: A hearing assistance device to provide sound to the ear of a user, the device comprising a housing, hearing assistance electronics enclosed in the housing, an acoustic transducer adapted to be worn in the ear, a cable assembly adapted to connect the acoustic transducer to the hearing assistance electronics, a wireless communications receiver connected to the hearing assistance electronics, and an antenna comprising one or more conductors forming at least a portion of the cable assembly.Type: GrantFiled: October 20, 2014Date of Patent: December 6, 2016Assignee: Starkey Laboratories, Inc.Inventor: Jeffrey Paul Solum
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Patent number: 9508949Abstract: An organic light emitting device includes a first electrode, a second electrode, and two or more organic material layers provided between the first electrode and the second electrode. The organic material layer includes a light emitting layer, and a mixed layer including one or more hole transfer materials and one or more electron transfer materials.Type: GrantFiled: July 18, 2013Date of Patent: November 29, 2016Assignee: LG DISPLAY CO., LTD.Inventors: Wonik Jeong, Jeamin Moon, Yun Hye Hahm, Jina You