Abstract: A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: According to embodiments described in the specification, a method and apparatus for managing memory in a mobile electronic device are provided. The method comprises: receiving a request to install an application; receiving at least one indication of data intended to be maintained in a shared cache; determining, based on the at least one indication, whether data corresponding to the intended data exists in the shared cache; upon a negative determination, writing the intended data to the shared cache; and repeating the receiving at least one indication, the determining and the writing for at least one additional application.

Abstract: Disclosed is a method for accessing a non-volatile memory device using a flash translation layer. The method includes receiving a write request for data from a file system and recording the data in the non-volatile memory device in response to the write request. The flash translation layer is informed whether a confirm mark for the data is recorded or not from the file system.

Abstract: A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Abstract: A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is selected based at least in part on the associated error rate. The unified cache is configured in accordance with the selected combination for execution of the application-unit.

Abstract: A system for normalizing capacity utilization within virtual storage pools includes collecting utilization statistics across individual storage devices that are members of a virtualized storage pool. Using the pool utilization level statistics, pool members may be assigned a score and, according to that score, may be marked as source, target or neutral members. Based on the scores of each pool member, data may be migrated among pool members, in particular, from source members to target members. The process may be iterative such that the statistics and scores may be used only to perform a fraction of the data movement that would be needed to normalize the storage pool before the scores are then recalculated. In this way, the system may dynamically adapt to changing conditions within the pool such as device additions, removals and inefficient striping of new data.

Abstract: A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based on the profile, an optimized layout of the lines in the code is computed, and the lines of the program are re-ordered in accordance with the optimized layout while continuing to execute the program.

Abstract: Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access.

Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Abstract: A system includes a source storage device, a target storage device, a host coupled to the source storage device and the target storage device, and a first migration device coupled to the source storage device and the target storage device. The first migration device includes a first virtual storage device. The first migration device is configured to migrate data from the source storage device to the target storage device, and the first virtual storage device is configured to receive write access requests for the data from the host during the data migration and send the access request to the source storage device and target storage device.

Abstract: A flash memory system having the capability of streaming data directly from flash memory to the interface of a host computer in order to substantially reduce latency of to-host transfers, while also maintaining the capabilities for caching and overlapped flash I/O provided by RAM DMA transfers. When data is read from the flash memory, the data is transferred into the RAM buffer and at the option of the memory controller, directly (via an intermediate FIFO) to the host interface. This results in a desirable reduction in the latency of data transfer because as soon as the first byte of data is read from the flash memory by the DMA engine, the data will be transferred directly to the host interface. Because the data is also being transferred to the buffer RAM, preferred embodiments of the present invention still provide the advantages of using an intermediate transfer buffer.

Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Abstract: An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.

Abstract: A method of configuring a cache includes identifying a plurality of cache configurations of a configurable cache for a processor-executable application unit. Each configuration has an associated error rate. A selected configuration is selected based at least in part on the associated error rate. The configurable cache is configured in accordance with the selected configuration for execution of the application-unit.

Abstract: A data protecting method for a portable memory storage apparatus is provided. The method includes determining whether a mode signal is at a data protecting mode, and performing a file hiding procedure to change a file allocation table if the mode signal is at the data protecting mode, wherein a host system coupled to the portable memory storage device is allowed to only access a portion of logical addresses of the portable memory storage apparatus according to the changed file allocation table and files stored in the portable memory storage apparatus before the file hiding procedure are written into another portion of the logical addresses. Additionally, the method still includes performing a file showing procedure to change the file allocation table if the mode signal is not at the data protecting mode, wherein the host system may access all the logical addresses according to the changed file allocation table.

Abstract: An approach is provided for providing an application-level cache. A caching application configures at least one memory of a mobile terminal into an application-level cache with a locked region and a floating region. The caching application then causes, at least in part, actions that result in caching, into each of the locked region and the floating region, of data items that are anticipated to be requested via an application of the mobile terminal.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: A storage device has two connectors for transferring data files: a first connector through which data files can be transferred at an accelerated speed, and a second connector through which data files can be transferred at a conventional speed. According to the present disclosure a user can select the speed (i.e., “normal speed” or “accelerated speed”) at which s/he wants to transfer a data file from a host to the storage device, and vice versa, by connecting the host to the proper connector of the storage device. The first connector is internally connected to a plurality of controllers that facilitate data transfers at the accelerated speed, and the second connector is internally connected to a controller that facilitates data transfers at the normal speed.

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.