Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Abstract: Embodiments of the invention provide a storage subsystem comprising a non-volatile solid-state memory array and a system operation module for managing memory operations. The system operation module is configured to store system operation data in a data structure that includes linked lists for storing system operation data, with at least some lists including entries referencing blocks in the solid-state memory array belonging to a category. The system operation module is further configured to (1) move a particular entry from a first linked list to a second linked list when a block referenced by the particular entry in the first linked list has met a condition for being classified in a new category that is different from that of the blocks referenced by entries in the first linked list, and (2) update entries within the first and second linked lists so that the dependencies in the linked lists are maintained.

Abstract: An integrated memory controller (IMC) may sit on the main CPU bus or a high speed system peripheral bus and couple to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for format definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation.

Abstract: A virtual disk can be created by using data from critical sectors of a primary physical disk. The creation of a virtual disk involves receiving sector numbers and corresponding data for critical sectors of a primary physical disk on a primary computing system, creating a virtual disk that comprises sectors, and writing data from the critical sectors of the primary physical disk into respective sectors of the virtual disk.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions.

Abstract: A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part of a data request, where the ID field has a line ID sub-field that represents a line ID value that uniquely identifies a particular cache line (or subset of cache lines) in the master, where the memory returns the line ID value back to the master along with the retrieved data. The master uses the line ID value to identify the cache line into which the retrieved data is to be stored. In this way, the master does not need to maintain a queue of address buffers to retain the addresses for data requests currently being processed, where the size of the queue limits the number of parallel in-service data requests by the master.

Abstract: In recent years, data life cycle management, in which data is relocated from, for example, a new storage sub-system to an older storage sub-system in accordance with how new the data is or the frequency of use of the data, has become important. One technology for achieving data life cycle management is technology for migrating the contents of a storage area (“volume”) of a storage sub-system to another volume without affecting the host computer that uses the volume. In the present invention, when an associated source volume (for example, the source volume in a copy pair association) of a pair of associated volumes is migrated, migration of an associated destination volume (for example, the target volume in the copy pair association) is also controlled. In this way, it is possible to control the migration of a pair (or a group) of associated volumes in accordance with the user's requirements.

Abstract: Difference information between two snapshots from a first point-in-time snapshot, which has been copied, to an N.sup.th point-in-time snapshot, which constitutes the latest point-in-time snapshot, is acquired to a memory module. The memory module stores two or more pieces of difference information. The two or more pieces of difference information comprise difference information that shows the difference between a first point-in-time snapshot and any snapshot other than the first point-in-time snapshot of N snapshots. Copy difference information, which is information that shows the difference between the first point-in-time snapshot and a specified snapshot from among N snapshots, and which is used in copying the specified snapshot, is created on the basis of the two or more pieces of difference information.

Abstract: After serially receiving several MSBs of the address, a microcontroller may determine whether a write operation is occurring in the same particular partition. If it is determined that a write operation is not occurring in the same partition, then the microcontroller may immediately perform the read operation. If a write operation is occurring, however, then the microcontroller may first begin to interrupt the write operation before beginning the read operation.

Abstract: Secure marshaling of data via one or more intermediate processes is provided. A source process may create a named shared memory section resulting in a first handle to the shared memory section. The source process may populate the shared memory section with information. An access control list may secure the shared memory section by preventing the one or more intermediate processes from accessing content of the shared memory section, while allowing a target process to access the content. The first handle and a name of the shared memory section may be marshaled to a first intermediate process resulting in a respective new handle to the shared memory section. A last intermediate process may marshal the name to a target process, which may use the name to obtain access to the content of the shared memory section.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up.

Abstract: A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address.

Abstract: Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal.

Abstract: A method include forming an initial bitmap from the de-duplicated data on virtual volumes, sorting discrete blocks according to frequency of occurrence to form a revised bitmap to first include a plurality of most common discrete blocks, creating a physical volume map from the revised bitmap, reviewing, from the physical volume map, an initial virtual volume of the virtual volumes contained on a corresponding original physical volume, to determine whether moving the initial virtual volume to a different physical volume reduces the total number of data blocks in the physical volume map, deleting the initial virtual volume from its corresponding original physical volume and adding the initial virtual volume to the different original physical volume to create a revised physical volume map including revised physical volumes, and writing the revised physical volumes to the target set of physical media using the revised physical volume map.