Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.
Type:
Grant
Filed:
November 18, 2009
Date of Patent:
September 24, 2013
Assignee:
Microsoft Corporation
Inventors:
Engin Ipek, Thomas Moscibroda, Douglas C. Burger, Edmund B. Nightingale, Jeremy P. Condit
Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
Type:
Grant
Filed:
June 4, 2012
Date of Patent:
September 24, 2013
Assignee:
International Business Machines Corporation
Inventors:
Gordon B. Bell, Gordon T. Davis, Jeffrey H. Derby, Anil Krishna, Srinivasan Ramani, Ken Vu, Steve Woolet
Abstract: A host device includes a first file system, and a storage device includes a plurality of memory units and a plurality of controllers. While the host device is operative coupled to the storage device, the host device creates a second file system corresponding to the storage device and copies host content from the first file system to the second file system. The second file system is segmented into a plurality of segments, each of the plurality of segments being uniquely associated with a particular one of the plurality of controllers. The host device selects a data transfer rate to write the host content from the second file system to the storage device.
Type:
Grant
Filed:
September 5, 2012
Date of Patent:
September 17, 2013
Assignee:
Sandisk IL Ltd.
Inventors:
Judah Gamliel Hahn, Donald Ray Bryant-Rich
Abstract: A data storage system stores logical data object(s), each identified by a logical identifier. A control is configured to assign a unique WORM (Write Once Read Many) identifier to the logical data object, and stores the unique WORM identifier as associated with the logical identifier, in a database maintained by the control so as to be persistent. Data storage is configured to write the logical data object with a header with the unique WORM identifier. The control, in order to allow the logical data object to be accessed externally to the control, requires matching the unique WORM identifier in the header of a logical data object to the unique WORM identifier of the persistent database for the logical object. The unique WORM identifier is formed of a checksum hash value related to nonce fields comprising at least the logical identifier of the logical data object, and an incrementing token.
Type:
Grant
Filed:
July 18, 2012
Date of Patent:
September 17, 2013
Assignee:
International Business Machines Corporation
Inventors:
Thomas William Bish, Jonathan Wayner Peake, Mark Albert Reid, Joseph M Swingler
Abstract: In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.
Type:
Grant
Filed:
January 4, 2011
Date of Patent:
September 10, 2013
Assignee:
International Business Machines Corporation
Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
Type:
Grant
Filed:
December 17, 2010
Date of Patent:
September 10, 2013
Assignee:
Intel Corporation
Inventors:
Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers
Abstract: A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.
Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.
Type:
Grant
Filed:
November 6, 2009
Date of Patent:
August 20, 2013
Assignee:
Pegasystems Inc.
Inventors:
John Clinton, Timothy Joseph Martel, Bachir Mohamed Berrachedi
Abstract: A method of duplicating data to multiple random accessible storage devices has steps of reading one segment of source data having multiple segments, continuously detecting newly-connected random accessible storage devices, duplicating same segments to all connected random accessible storage devices, stopping duplicating the source data to any random accessible storage device that has stored all segments of the source data and repeating the steps from the beginning. When duplicating the source data to all connected random accessible storage devices, same segments of the source data are written to all connected random accessible storage devices. Therefore, a single writing task is proceeded in each writing session. The source data can be written to all random accessible storage devices at high speed. Consequently, efficiency of asynchronously duplicating data to multiple random accessible storage devices is increased.
Abstract: A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.
Abstract: Embodiments of the invention relate to a storage system cache with flash memory units organized in a RAID configuration. An aspect of the invention includes a storage system with a storage cache that includes flash memory units organized in an array configuration. The storage system further includes an array controller that manages data access and data operations for the flash memory units and organizes data as full array stripes. The storage system also includes a storage cache controller, that includes a block line manager that buffers write data to be cached for a write operation until the storage cache controller has accumulated an array band, and commits write data to the array controller as full array stripes. The storage cache controller determines whether to store write data for a write in the storage cache and/or in the primary storage device and whether to access read data from the storage cache or from the primary storage device.
Type:
Grant
Filed:
December 29, 2010
Date of Patent:
July 9, 2013
Assignee:
International Business Machines Corporation
Inventors:
Steven Robert Hetzler, Daniel Felix Smith
Abstract: Allocation of virtual disk volumes of a size designated by the computer manager to a virtual computer and accessiblity from the virtual computer to the virtual disk voumes without requiring intervention by a hypervisor are to be achieved. In a computer, at least one virtual computer to be in execution on the computer, and a computer system in which the virtual computer has volumes for holding data, a virtualization mechanism has a virtual volume allocating unit and a virtual volume information supplying unit, and the virtual computer has a virtual volume driver for converting positional information on virtual volumes. Additionally, the virtualization mechanism holds the virtual volume information together with defining information for the virtual computer to which the virtual volumes have been allocated.
Abstract: A disk array control apparatus controls writing of data onto an array of N storage devices such as disk drives, where N is an integer of 3 or greater. Each storage device writes data with a granularity of a sector having a predetermined sector size. The apparatus writes data with a granularity of a transfer unit having a transfer size which is T times the sector size, where T is a plural integer greater than (N?1). The apparatus is allows writing to an array of storage devices for which (N?1) is not a factor of T. In particular, the apparatus divides each transfer unit of data into plural stripes each consisting of a respective plural number of sectors of data having the sector size, the stripes each consisting of at most (N?1) sectors and at least one of the stripes consisting of less than (N?1) sectors, and calculates, in respect of each stripe, a parity sector of parity data. The sectors of data and the parity sector representing the parity of each stripe are written onto different storage devices.
Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.
Abstract: In recent years reducing the operating cost of storage devices (hereafter, also referred to as storage sub-systems) has been an important task for the management of storage systems. As one method for solving this task, data life cycle management, in which data is relocated from, for example, a new storage sub-system to an older storage sub-system in accordance with how new the data is or the frequency of use of the data, has become important. One technology for achieving data life cycle management is technology for migrating the contents of a storage area (hereafter referred to as “volume”) of a storage sub-system to another volume without affecting the host computer that uses the volume. In the present invention, when an associated source volume (for example, the source volume in a copy pair association) of a pair of associated volumes (or groups) is migrated, migration of an associated destination volume (for example, the target volume in the copy pair association) is also controlled.
Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.
Abstract: A method of recording, and an apparatus for recording, data on a write-once disc, and the write-once disc used with the method and the apparatus. The write-once disc includes a plurality of update areas in which to record a predetermined type of updated information, at least one main access information area (AIA) in which to record main access information (AI), the main AI indicating a final update area in which finally updated information is recorded, among the plurality of update areas, and at least one sub AIA in which to record sub AI, the sub AI indicating a location of the finally updated information recorded in the final update area.
Abstract: Methods of operating memory devices, and memory devices configured to perform such methods, including reading Erase Block Management (EBM) data from an erase block of an array of memory cells. The EBM data, corresponding to a state of the particular erase block, is stored in control data spaces of a subset of sectors of the particular erase block.
Abstract: An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
Type:
Grant
Filed:
December 16, 2009
Date of Patent:
March 26, 2013
Assignee:
Intel Corporation
Inventors:
Simon C. Steely, Jr., William C. Hasenplaugh, Aamer Jaleel, George Z. Chrysos
Abstract: In a file server, a file system is built upon a volume of data storage. The file system includes multiple cylinder groups. Each cylinder group includes file system blocks. The file system blocks include allocated blocks and free blocks. The volume includes slices of storage, and each slice stores at least one of the cylinder groups. A hierarchical slice map has a top level that includes a count of free blocks in the file system, an upper level that includes a count of free blocks in groups of the slices, an intermediate level that includes a count of the free blocks in sub-groups of the slices, and a bottom level that includes a count of the free blocks in each slice of storage. To find a free block for allocation to a file, the slice map hierarchy is searched in a top-down fashion.
Type:
Grant
Filed:
November 19, 2010
Date of Patent:
March 26, 2013
Assignee:
EMC Corporation
Inventors:
Michael D. Scheer, Jean-Pierre Bono, Morgan Clark, Hongliang Tang, Sairam Veeraswamy, Pranit Sethi, Alexander S. Mathews