Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.

Abstract: Methods and apparatus for compensating offsets in a read signal generated by a sensor associated with a probe of a local-probe data storage device during read-scanning by the probe of bit-positions on a storage surface. An apparatus comprises a generator for generating an offset compensation signal, and a subtraction stage for producing an output signal dependent on the difference between the offset compensation signal and the sensor read signal at each bit-position. In some embodiments, an offset signal generator generates an offset compensation signal dependent upon a predetermined measurement of the sensor read signal. In another aspect the offset signal generator low-pass filters the sensor read signal during read scanning to generate the offset compensation signal. Particular embodiments also include a secondary offset compensation stage for applying additional offset compensation techniques to the output signal from the subtraction stage.

Abstract: A look-ahead delta sigma modulator reduces and simplifies the computations used to generate quantizer output values. Superposition can be applied to a loop filter response of the look-ahead delta sigma modulator. By superposition, the complete loop filter response for each output candidate vector equals the difference between a forced pattern response and a natural input signal response. The forced pattern response of the loop filter can be determined from the response to each output candidate vector with an input signal set to zero and loop filter state variables initially set to zero when determining the loop filter response for each output candidate vector. The natural input signal response of the loop filter can be determined from the response to each input signal vector with feedback data set to zero. The forced pattern response is independent of the input signal data and can be determined once for all input signal vectors Xt.

Abstract: A method, apparatus, and computer-readable medium for compressing and decompressing an input data stream utilizing multiple dictionaries is provided. According the method for compressing data, a string and a character are read from the input data stream. A determination is made as to whether the string plus character are contained in a first or second dictionary. If the string plus character is in either dictionary, a next character is added to the string. If the string plus character is not in either dictionary, a code or character is output. A determination is then made as to whether the input word and string is a two character word. If so, a new code is added to the first dictionary corresponding to the two character word. Otherwise, a new code is added to the second dictionary for the string and character.

Abstract: A method and system using a single interleaver at a either a receiving device or a transmitting device where a first symbol set is read from the single interleaver and concurrently with a second symbol set is written to the single interleaver, and a controller that synchronizes the reading of the first symbol set from the interleaver and the writing of the second symbol set to the interleaver so that a particular symbol of the second symbol set is only written to a location of the interleaver after a particular symbol of the first symbol set has been read from the location. The controller may switch between orders, e.g., row order and column order, of reading and/or writing symbols to the single interleaver when all of the symbols for a particular set of symbols associated with the single interleaver have been read, according to another embodiment.

Abstract: In an LVDS system for converting N types (for example N=3) of parallel signals into serial signals and sending/receiving the converted serial signals between a driver and a receiver through M (M?N) signal lines, a sequencer 11 for selecting drivers 10a to 10c to be used in accordance with the number of signal lines used for transmission/reception and a reception-side sequencer for selecting a receiver to be used in accordance with the number of signal lines M used for transmission/reception are included to perform transmission/reception by using the driver and receiver selected by the both sequencers. Thus, it is possible to select the number of channels and a data rate optimum for the impedance of a signal line without fixing the number of signal lines used for transmission/reception.

Abstract: An apparatus uses a “self-organizing” method to eliminate or at least partially compensate for undesired or unexpected threshold errors encountered in analog-to-digital conversions. The self-organizing feature results in a relatively good, such as an optimal, spacing of a plurality of comparator thresholds even in the presence of relatively large comparator offsets, reference offsets, or other system offsets. Advantageously, the self-organizing techniques can be used without a special starting point for the thresholds. The self-organizing techniques can be used applied to at least portions of any analog-to-digital converter ADC that uses comparators, such as flash ADCs, pipeline ADCs, and sub-ranging ADCs.

Abstract: A system for training a linearization compensation model includes a tone generator for providing at least two different RF tones, receiver path components for processing the RF tones, an analog-to-digital converter for converting the processed RF tones into digital signals, and a processor for using the digital signals to generate the linearization error compensation model. The resulting compensation model is particularly useful in a linearization system which includes a receiver for measuring a signal, an electro-optical modulator configured for converting the measured signal to an optical signal, an optical-electrical detector configured for converting the optical signal to an analog electrical signal, an analog-to-digital converter for converting the analog electrical signal into a digital signal with the processor being used for removing linearization errors from the digital signal.

Abstract: An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to a couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Abstract: In one embodiment, a micro electromechanical system (MEMS) driver circuit receives a pulse-width modulated (PWM) signal and uses it to control a voltage at a MEMS cell. The driver circuit further includes a current source, a capacitor, and a reset circuit that can discharge the capacitor. The voltage at the MEMS cell can be controlled in proportion to the pulse width of the PWM signal. In another embodiment disclosed, a MEMS driver circuit receives a first PWM signal and a second PWM signal. Each PWM signal is coupled to a current source. One current source can provide a course current control and the other current source can provide fine current control. The driver circuit can further include a capacitor and a reset circuit for discharging the capacitor. The voltage at the MEMS cell can be controlled in proportion to a summation of the first and second current sources. According to another aspect of the embodiments, a method of controlling a voltage at a MEMS cell is disclosed.

Abstract: There are provided a variable-length code decoding apparatus and method which can perform high-speed decoding processing without decreasing an image size and frame rate. A variable-length code decoding apparatus of this invention decodes a variable-length code containing a prefix and a suffix. This apparatus includes a prefix decoding unit which decodes the prefix of an input variable-length code and outputs a symbol and prefix length corresponding to the prefix, a suffix shifter unit which supplies the suffix on the basis of the prefix length output from the prefix decoding unit, and a symbol decoding unit which decodes a symbol corresponding to a variable-length code on the basis of the symbol corresponding to the prefix which is output from the prefix decoding unit, the suffix supplied by the suffix shifter unit, and a suffix length acquired in advance.

Abstract: Signal driving circuits with high driving capability and precise analog output voltage level, by outputting analog voltages through analog buffers and directly outputting voltages from digital-to-analog converters in turn. A digital-to-analog converter generates a first analog voltage according to digital data. An output circuit selectively either outputs a second analog voltage according to the first analog voltage by an analog buffer to a load or outputs the first analog voltage to the load directly.

Abstract: In order to decrease a required memory capacity of a line memory and to efficiently compress an image by coding, even when character information is contained in a high-resolution image, each time the block of an image that is equally divided into M (M: an arbitrary integer greater than 1) blocks in the horizontal direction is updated, difference data between color code data at corresponding pixel positions in the horizontal line and the adjacent immediately-preceding horizontal line with respect to each horizontal line within the block is detected by a line memory and an exclusive-OR circuit.

Abstract: An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential comparator is provided for generating digital values to which the digital bits correspond. A pair of digital-to-analog converters are provided for generating, via successive approximation, a differential feedback analog signal based on bits previously generated by the differential comparator. The analog-to-digital converter compares the differential feedback analog signal to the input analog signal, and based on the comparison generates a digital value that corresponds to a digital bit. In the method of the invention, an analog signal is converted to a digital value using the analog-to-digital converter, and a pair of digital-to-analog converters each generate, via successive approximation, a differential feedback analog signal that is applied to a differential comparator for comparison to the input analog signal being digitized.

Abstract: Data destined for a client is compressed at a server in a manner that produces a compressed data string that can be searched in its compressed state. The server constructs a code table that assigns codes from a standard code set (e.g., ASCII code set) that are normally unused to selected character pairs in the data string (e.g., the most frequently occurring character pairs). During compression, the selected character pairs are replaced with the corresponding codes. Identifiers are inserted into the compressed data string to separate substrings. To search the compressed data string at the client, a search query is compressed and compared to the compressed substrings. The substring identifiers are used to quickly locate each successive compressed substring. When a match is found, the matching substring is decompressed by replacing the code in the compressed substring with the corresponding character pair in the code table.

Abstract: The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range expansion facility by means of a special design for the comparison circuit in the first converter stage. The comparison circuits in the analog/digital converter allow decisions to be made for the further signal processing previously in a preceding time period. Two respective generator circuits in successive converter stages share one amplifier. This reduces the amount of space taken up and current drawn, increases the clock rate and simplifies signal processing for signals with high levels.

Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Abstract: Data destined for a client is compressed at a server in a manner that produces a compressed data string that can be searched in its compressed state. The server constructs a code table that assigns codes from a standard code set (e.g., ASCII code set) that are normally unused to selected character pairs in the data string (e.g., the most frequently occurring character pairs). During compression, the selected character pairs are replaced with the corresponding codes. Identifiers are inserted into the compressed data string to separate substrings. To search the compressed data string at the client, a search query is compressed and compared to the compressed substrings. The substring identifiers are used to quickly locate each successive compressed substring. When a match is found, the matching substring is decompressed by replacing the code in the compressed substring with the corresponding character pair in the code table.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: Systems, methods and devices are described for placing a controlled device into a desired operating state in response to the position of a multi-position actuator. Two or more switch contacts provide input signals representative of the position of the actuator. Control logic then determines the desired state for the controlled device based upon the input signals received. The desired operating state is determined from any number of operating states defined by the input values. In various embodiments, ternary switching may be used in combination with binary switching to efficiently implement multi-state rotary or linear switches capable of identifying six, twelve, eighteen or any other number of switchable states.