Abstract: A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.

Abstract: An analog-to-digital converter includes a switched capacitor circuit, an analog-to-digital conversion circuit, and a constant current circuit. The switched capacitor circuit includes first and second input terminals for a differential input, and is configured to sample an analog voltage of the differential input. The analog-to-digital conversion circuit is connected to output terminals of the switched capacitor circuit, and configured to convert the sampled analog voltage into a digital signal and output the digital signal. The constant current circuit is connected to at least one of the first and second input terminals.

Abstract: A method for compressing flow data, including: constructing multiple line segments according to flow data and a predefined maximum error that are acquired; obtaining a target piecewise linear function according to the multiple line segments, where the target piecewise linear function includes multiple linear functions, and an intersection set of value ranges of independent variables of every two linear functions among the multiple linear functions includes a maximum of one value; and outputting a reference data point according to the target piecewise linear function, where the reference data point includes a point of continuity and a point of discontinuity of the target piecewise linear function. In this way, a maximum error, a target piecewise linear function is further determined according to the multiple line segments, and a point of continuity and a point of discontinuity of the target piecewise linear function are used to represent compressed flow data.

Abstract: A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.

Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT).

Abstract: Data compression/decompression methods and data compressor/de-compressor are provided. The data compression method includes the steps of scaling an input signal to generate a scaled signal; transmitting the scaled signal to a differentiator and an assembler; differentiating the scaled signal and a prior signal to generate a differentiation signal detecting zero bits of the differentiation signal to generate a zero range control signal and a zero range control word; refining the differentiation signal according to the zero range control signal to generate a refined signal; and determining to combine the zero range control word with the scaled signal or combine the zero range control word with the refined signal according to the zero range control word to generate a compressed signal.

Abstract: A RFID system, according to one embodiment, includes: a plurality of radiating elements, a transmission line, and power dividers coupling the plurality of radiating elements to the transmission line. The power dividers are coupled along the transmission line, and are configured such that they provide an equal distribution of power between each of the plurality of radiating elements. Moreover, an input impedance of each of the power dividers is about equal to an impedance of the transmission line.

Abstract: An encoder for encoding input data to generate corresponding encoded data includes data processing hardware which is operable: to determine at least partial reoccurrences of data blocks or data packets within the input data, wherein the data blocks or data packets include a plurality of bytes; to employ at least one reference symbol to relate reoccurrences of mutually similar data blocks or data packets and/or to indicate whether or not there are reoccurrences of mutually similar data blocks or data packets within the input data; to employ a plurality of change symbols, for example a plurality of mask bits, to indicate changed and unchanged data elements of partial reoccurrences of data blocks or data packets within the input data and a change of data values of changed data elements; and to encode the at least one reference symbol and the plurality of change symbols into the encoded data.

Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

Abstract: A data converter is disclosed. The data converter includes a loop-filter, a quantizer, an analog dynamic element matching (DEM) shuffler, a digital DEM shuffler and a feedback digital-to-analog converter. The loop-filter receives analog signals from an analog input. The quantizer then converts the filtered analog signals from the loop-filter to digital signals at a digital output. The analog DEM shuffler shuffles a set of analog threshold levels of the quantizer to yield a set of partially shuffled digital data at an output of the quantizer. The digital DEM shuffler shuffles the set of partially shuffled digital data from the output of the quantizer to yield a set of shuffled digital data. The feedback digital-to-analog converter converts the set of shuffled digital data to a set of analog data to be fed back to the loop-filter.

Abstract: Comparator circuits suitable for use in a column-parallel single-slope ADC comprise a comparator, an input voltage sampling switch connected between an input voltage Vin and a first node, and a sampling capacitor connected between the first and second nodes and which stores a voltage which varies with Vin when the sampling switch is closed. A first reset switch is connected between the second node and a reset voltage, an isolation buffer is coupled between the second node and a comparator input, and a voltage ramp switch applies a voltage ramp Vramp to the first node when closed. The comparator output toggles when Vramp exceeds Vin, with the isolation buffer maintaining a nearly constant capacitive load on Vramp. A ‘ramp disconnect’ feature can be used to increase the circuit's input range, and a dummy capacitor can be employed to maintain a constant capacitance on Vramp.

Abstract: A multiband antenna includes a feeding element connected to a feeding point, a radiating element functioning as a radiating conductor, the radiating element being positioned apart from the feeding element and fed with electric power by electromagnetically coupling to the feeding element, a ground plane, and a non-feeding element being positioned close to the radiating element and connected to the ground plane via a reactance element. The reactance element has a reactance that causes the multiband antenna to match with a frequency other than a resonance frequency of a resonance mode of the radiating element.

Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

Abstract: A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.

Abstract: A digital to analog conversion circuit, DAC, comprises a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate. The DAC further comprises a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports.

Abstract: In a multilayer substrate, eight front-side antenna portions and eight back-side antenna portions are disposed. Front-side radiation elements in the front-side antenna portions and back-side radiation elements in the back-side antenna portions are arranged in a staggered pattern when being vertically projected onto an back side of the multilayer substrate. The front-side radiation elements are disposed on a front side of the multilayer substrate, and a front-side ground layer is formed near the back side of the multilayer substrate. On the other hand, the back-side radiation elements are disposed on the back side of the multilayer substrate, and a back-side ground layer is formed near the front side of the multilayer substrate. The front-side radiation element and the back-side radiation element are disposed so as not to overlap each other when being vertically projected onto the back side of the multilayer substrate.

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract: An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.

Abstract: In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output node of the reference buffer wherein the first switched capacitor comprises at least one first capacitor and at least one first switch may be provided. The method may include coupling a passive network to the output node of the reference buffer in response to a presence of a condition for encountering the voltage kickback in order to create an approximately equal and opposite voltage kickforward by the passive network to at least partially neutralize the voltage kickback.

Abstract: A substrate includes a dielectric plate and a conductive layer formed on both surfaces of the dielectric plate, and a first cutout is formed in the conductive layer on both surfaces of the substrate so as to extend inward from part of a first edge of the substrate. A first radiation electrode is connected to the conductive layer at a first point located on an outer peripheral line of the first cutout. A first reflector plate is disposed in a location further inward in the substrate from the first edge than the first point. The reflector plate is electrically connected to the conductive layer, and faces toward the first point. Thus an antenna device that is suited to miniaturization and that is capable of increasing directivity is provided.