Abstract: An exemplary circuit includes a tracking circuit, a current estimator, a switch control logic, and a switching load circuit. The tracking circuit tracks a digital output signal of a delta-sigma modulator (DSM) and provides a tracking signal representing an average of the digital output signal during a time period. The current estimator determines an amount of loading to be applied to positive and negative reference voltages based on the tracking signal. The switching load circuit is coupled to positive and negative reference voltages of the DSM, the switching load circuit connects a selected amount of loading to the positive and negative reference voltages in response to a control signal to balance a reference load current applied to the DSM. The switch control logic provides the control signal to the switching load circuit based on the determined amount of loading to be applied to the positive and negative reference voltages.

Abstract: According to one embodiment, a signal conversion device includes a first serial-parallel converter, a second serial-parallel converter, a first buffer, a second buffer, a clock generator, and a selection output part. The first serial-parallel converter receives a first serial signal, generates a first clock signal I, generates a first parallel signal, and generates first status information including first information. The second serial-parallel converter receives a second serial signal, generates a second clock signal, generates a second parallel signal, and generates second status information including second information. The first buffer stores the first parallel signal. The second buffer stores the second parallel signal. The clock generator generates an output clock signal. The selection output part uses the first status information and the second status information to output a signal based on one parallel signal of the first parallel signal or the second parallel signal.

Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.

Abstract: The present disclosure, related to the technical field of fingerprint identification, discloses a ramp wave generation circuit, a digital-to-analog conversion circuit, and a fingerprint identification system. The ramp wave generation circuit comprises: an integrating circuit, configured to output a ramp wave signal; a signal regulation circuit, comprising a feedback control loop and a transconductance amplifier connected in series, wherein the feedback control loop monitors the ramp wave signal output by the integrating circuit, and outputs a regulation control signal to the transconductance amplifier, the transconductance amplifier corrects, according to the regulation control signal, a ramp wave signal output by the integrating circuit within a next period; and a voltage generation circuit, configured to respectively output a reference voltage signal to the integrating circuit and the signal regulation circuit.

Abstract: Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.

Abstract: The present invention relates to the communications field, and in particular, to an antenna system. The antenna system includes: a transmit antenna, a receive antenna, a radome above the transmit antenna and the receive antenna, and a reflector within the radome, where a signal received by the receive antenna after a transmitted signal of the transmit antenna is reflected by the reflector offsets an intra-frequency interference signal generated because the transmitted signal of the transmit antenna is directly received by the receive antenna. As a result, according to the embodiments of the present invention, the intra-frequency interference signal of the transmit antenna to the receive antenna may be eliminated without increasing the number of antennas and a distance between antennas.

Abstract: To reduce the overall reference charge needed to perform operations, analog-to-digital converters can maintain reference voltage connections of the bit trial capacitors of the digital-to-analog converter (DAC) from the end of a current conversion to just prior to the beginning of the next acquisition phase. At the start of the next acquisition phase, the bottom plates of the bit trial capacitors of the DAC can be shorted to generate a common mode voltage. As the conversion phase begins, the bottom plates of the sampling capacitors are disconnected from the input voltage and the bottom plates of each bit trial capacitor are shorted to generate input common-mode voltage. As bit trials progress, the shorts between the bottom plates of the bit trial capacitors are removed and the bit trial results are applied to the bottom plates of the bit trial capacitors.

Abstract: The present application discloses a data transmission method and apparatus. A specific implementation of the method includes: receiving to-be-transmitted data sent from an information sending end, and determining a sending coding type of the to-be-transmitted data; determining a receiving coding type of an information receiving end receiving the to-be-transmitted data; converting the to-be-transmitted data from the sending coding type to the receiving coding type using a preset transcoding model, to obtain transcoded transmission data, the transcoding model representing a corresponding relationship between the sending coding type and the receiving coding type; and sending the transcoded transmission data to the information receiving end. This implementation improves the data transmission efficiency.

Abstract: A quantizer including passive summers, dynamic comparators and a clock generator. Each passive summer samples the input voltages and a reference voltage scaled by one of multiple graduated gains, and subtracts the scaled reference voltage from the sum of the input voltages. The graduated gains divide a predetermined voltage range into multiple voltage subranges, each between sequential pairs of the passive summers. The dynamic comparators compare each sequential pair of passive summer output voltages according to multiple splitting ratios and provide corresponding quantization bits. The dynamic comparators are activated in groups to reduce comparator kickback. Each dynamic comparator recharges the passive summer output voltages coupled to its inputs back to their initial voltage values to reduce kickback residual. The passive summers eliminate the need for a resistor string to generate the reference voltages.

Abstract: This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT).

Abstract: A system, method and product for providing data compression and decompression. A method is disclosed that includes: utilizing a CPU to perform a matching-bytes search, byte-oriented search result coding, and content analysis on a set of raw data to generate a set of initially compressed data; forwarding the set of initially compressed data from the CPU to a hardware accelerator; utilizing the hardware accelerator to perform search result re-coding, table construction, and encoding to generate a set of further compressed data; and forwarding the set of further compressed data back to the CPU.

Abstract: An apparatus is described herein. The apparatus comprises an accumulator, a controller, and a convolutional neural network. The accumulator is to accumulate a plurality of values within a predetermined bit width. The controller is to determine a parameter quantization and a data quantization. The convolutional neural network is adapted to the data quantization, wherein a quantization point is selected based on the parameter quantization, data quantization, and accumulator bit width.

Abstract: A method for pre-loading a SAR ADC with an initial value for a selected range of high-order bits. If the ADC resolves at either an upper or a lower limit set by the pre-loaded value, the ADC may discard the pre-loaded value and perform a full search. Alternatively, the ADC may perform one or more “bonus steps” before giving up and performing a full search.

Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.

Abstract: A system and method is provided for image sensing. The image sensing system includes a comparator for comparing an input signal representing a sensed light signal from at least one pixel of the image sensing system and a reference signal. The comparator includes at least one digital transistor.

Abstract: An application-specific integrated circuit comprises: analog inputs having analog-digital converters; at least one digital signal processor, which has input registers and output registers. The analog-digital converters sample and digitize input signals Si with sampling frequencies fSi and forward the digitized signals SDi with output frequencies fSD-out-i to the input registers of the digital signal processor. The digital signal processor processes the digitized signals SDi to m processed signals SPj and forwards such to the output registers of the digital signal processor. The digital signal processor has a clock frequency, wherein, furthermore, the signals of the output registers can be output, respectively read-out, with an output frequency. One or more of the frequencies is, respectively, variable, wherein especially one or more of the frequencies, respectively, variable independently of the others of the frequencies.

Abstract: DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.

Abstract: An apparatus is configured to extract a rightmost bit position of a target value based on input data and a complement of the input data, sequentially extract a bit position of the target value, and output the extracted bit position.

Abstract: A delay line-based time to digital converter includes: a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected; a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; and a timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value.